标签: fpga电子时钟

简易数字电子钟/*----------------------------------------------------------Engineer:zhrscut--CreateDate:--ModuleName:--ToolVersions:Quartus_II9.1--欢迎加入EEPW，FPGA开发板DIY活动--------------------------------------------------------*/moduleclock(seg,sel,rst_n,clk);inputclk;inputrst_n;output[7:0]seg;output[7:0]sel;//-----------------------------------------reg[7:0]seg_reg;reg[3:0]seg_buf;reg[7:0]sel_reg;reg[14:0]dis_counter;reg[24:0]time_counter;reg[3:0]dis_status;reg[7:0]hour,min,sec;regsec_flag;//-----------------------------------------always@(posedgeclk)begintime_counter=time_counter+1'b1;if(time_counter==25'd25_000_000)begintime_countersec_flagendendalways@(pose……