简易数字电子钟/*-------------------------------------------------------- -- Engineer: zhrscut -- Create Date: -- Module Name: -- Tool Versions: Quartus_II 9.1 -- 欢迎加入 EEPW，FPGA 开发板 DIY 活动 --------------------------------------------------------*/ module clock( seg,sel, rst_n,clk); input clk; input rst_n; output[7:0] seg; output[7:0] sel; //----------------------------------------- reg[7:0] seg_reg; reg[3:0] seg_buf; reg[7:0] sel_reg; reg[14:0] dis_counter; reg[24:0] time_counter; reg[3:0] dis_status; reg[7:0] hour,min,sec; reg sec_flag; //----------------------------------------- always@(posedge clk ) begin time_counter=time_counter+1'b1; if(time_counter==25'd25_000_000) begin time_counter sec_flag end end always@(pose……