标签: block

随着数据中心、人工智能、自动驾驶、5G、计算存储和先进测试等应用的数据量和数据流量不断增大，不仅需要引入高性能、高密度FPGA来发挥其并行计算和可编程硬件加速功能，而且还对大量数据在FPGA芯片内外流动提出了更高的要求。于是，在FPGA芯片中集成包括片上二维网络（2D NoC）和各种最新高速接口的新品类FPGA芯片应运而生，成为FPGA产业和相关应用的新热点。 拉开这场FPGA芯片创新大幕的是全球最大的独立FPGA技术和产品提供商Achronix半导体公司，其采用7nm工艺打造的AchronixSpeedster7t FPGA不仅拥有诸多高性能外围Hard IP，而且是全球首次在FPGA的逻辑阵列上集成了2D NoC，一经推出就在市场得到了积极的响应，并引来竞争对手的模仿和跟随。 Speedster7t这款专门针对人工智能/机器学习（AI / ML）和高带宽应用进行优化的高性能、高密度FPGA，包括了革命性的二维片上网络（2D NoC）、新型机器学习处理器（MLP）、400G以太网和PCIe Gen5端口，以及高带宽GDDR6和DDR4/5存储控制器。Speedster7t FPGA架构如图1所示。 图1 Speedster7t FPGA结构图 AchronixSpeedster7tFPGA除了在外围HardIP上都采用目前业内领先的大带宽高速率IP，在内部的可编程逻辑的架构中也做了大量的优化去进一步提高内部可编程逻辑的性能，从而适配外围IP超高带宽需求。本文首先谈谈Speedster7tFPGA的片上SRAM，也就是BlockRAM针对传统的结构所做出的一些优化。 Speedster7tFPGA中可编程逻辑的架构 Speedster7tFPGA中内部的可编程资源是按列排布，包括LUT、FF、ALU、MUX、MLP、BlockRAM、LogicRAM。如图2所示。 图2 Speedster7t FPGA可编程逻辑结构 其中MLP、BlockRAM、LogicRAM是集成在一起，他们之间的连接用的是专有的走线，不占用可编程逻辑走线资源，这样做的目的主要是为了提高性能，同时也可以节省可编程逻辑走线资源，这个架构对于AI，还有需要用到MLP的一些复杂算法的性能优化是非常明显的，在我们的MLP系列文章中会详细讲到，这里我们只重点说一下BlockRAM。 Speedster7tFPGA的BlockRAM特点 Speedster7t FPGA内部的BlockRAM是一个容量为72kbit的简单双端口RAM，有一个读端口，一个写端口。两个端口的时钟完全独立，并且可以完全独立的配置读写位宽。它可以灵活的配置成简单双端口RAM或者ROM。 BlockRAM的主要特性如表1所示。 表1 Block RAM的关键特性 BlockRAM框图如图3所示。 图3 BlockRAM内部结构 Speedster7tFPGA的BlockRAM级联结构 Speedster7tFPGA的BlockRAM最大的特点是增加了BlockRAM间的级联走线，级联走线是BRAM间专有的连线，不占用可编程逻辑的走线资源，可以极大的提升多个BlockRAM级联的性能。图4显示了BlockRAM间级联走线的架构。 图4 BlockRAM级联结构 由图4可以看出，读写地址线和数据线都有专有的级联线连接。这样的架构在一些场景中都会有应用，比如：需要从外部端口接收数据或者从GDDR6读数据去初始化大量BlockRAM的场景，AI的神经网络就是一个典型的应用，在每一层的卷积算法中，系统都会从GDDR6读出图像数据和权重数据放入每个引擎的BlockRAM中，引擎计算完毕以后再存入到GDDR6中供下一次运算使用。 有了这样的级联架构，我们在写入数据去初始化大量BlockRAM的时候不需要外部数据有很大的扇出，直接通过同一列BlockRAM的级联线就可以轻松完成，具体实现可以参考Achronix MLP_Conv2D参考设计。另外一个例子就是在需要多个BlockRAM去构成更大容量的RAM的时候，如果利用级联线可以大大提升系统的性能。我们针对这个专门做了一个工程比较一下，生成一个位宽64bit，深度16384的一个简单双端口RAM，需要用到16个BlockRAM。我们分别用专有级联线和内部可编程逻辑去拼深度两种方法来对比。可以看到用专有的级联线资源更省，而且性能有了很大的提高。 使用专有的级联线资源占用和性能： 使用可编程逻辑资源占用和性能： 后面我们会继续深入了解Speedster7t FPGA可编程逻辑的各种特性，并且会用一些例子来说明如何更高效的利用这些特性，以将Speedster7t这款业界首创的高数据带宽FPGA芯片与更多的创新智能化应用结合起来。 此外，Achronix也提供Speedcore嵌入式FPGA硅知识产权（IP）产品，用来帮助用户在应用规模进一步扩大后，去开发带有eFPGA逻辑阵列的ASIC或者SoC产品，它们由Achronix的ACE FPGA开发工具提供支持，从而可以重用FPGA开发成果，这是Achronix在率先引入2D NoC和MLP之外，另一个层面上的创新。 参考文献： Achronix website www.achronix.com Achronix Speedster7t IP component UG090

Cadence OrCAD Capture 创建自定义 Title Block，只要是逼格高一点的公司或设计团队都会这么做的。添加公司的Logo，公司名称，规范一点的还要放置图纸设计人员，评审人员的签名框等等。 这显然是Cadence OrCAD Capture自带的Title Block满足不了的，Cadence OrCAD Capture自带的Title Block保存在Cadence安装路径下，如： C:\Cadence\SPB_17.0\tools\capture\library\capsym.olb 这里 capsym.olb 就是包含Title Block的库文件，里边除了Title Block，还有电源、地符号，off page符号等。     创建自定义的Title Block与创建原理图符号类似，其也是保存在olb文件中。通过在olb文件上鼠标右键弹出菜单中选择“New Symbol”，然后在“New Symbol Properties”对话框中选择“Title Block”项来新建一个Title Block。         其实系统自带的Title Block已经满足了我们大部分的功能，我们只需要增加Logo及公司标题名称等部分，大可不必重新开始，直接在系统自带的Title Block上进行修改添加即可。 在原理图项目文件夹的“Design Cache”文件夹下保存有当前的Title Block文件，我们将其拷贝到我们的Library文件中，直接在上面进行修改。 在Library里双击Title Block，运用 Place line 来画线框，Place text 来放置文字信息，通过菜单栏 Place-Pictrue…来放置我们的LOGO。 我们还可以通过菜单 Options-Part Properties，来放置对应的Title Block 变量信息，例如：Page Name，Schematic Create Date等信息。   操作视频百度云分享猛击这里： http://pan.baidu.com/s/1kT3Xu9D   原创文章，转载请注明：  转载自  吴川斌的博客  http://www.mr-wu.cn/  本文链接地址:   Cadence OrCAD Capture 创建自定义 Title Block http://www.mr-wu.cn/how-to-create-title-block-in-orcad-cature/

In part 1 , Prakash Narain, CEO of Real Intent, related his early career and the primary steps that prepared him to start his own company. Then in part 2 , we talked about the early days of Real Intent and the impact that the dotcom boom and bust had on developing technology. At the end of the last segment, Narain talked about Real Intent's success with implied intent verification, but he wondered if it was a distraction from its broader goals. Now read on. Prakash Narain : What we were looking to pursue didn't materialise in the form we wanted, and we realised that our goals may have been a little too big. At the same time, success had materialized, and this became the way we were able to sustain ourselves. After that, we built our clock domain crossing tool, but in those days, there was not a big market for it. We still held the dream of building an automated, scalable, formal verification solution and helped drive standards we thought were necessary, such as SystemVerilog. There came a point where we decided that the combination of things we were trying to put together was not viable, so we had to make a choice. The choice was should we build highly complex systems, or should we build products that were scalable, lower-touch solutions. This changed us from being a technology-focused company to being a product-focused company. We would develop whatever formal technology was necessary to solve specific problems. EE Times : Do you think the original goal would have been realisable under ideal market conditions? Narain : We went away from the goal because we don't believe that it was realisable. Under perfect conditions, with the knowledge that I now have, I would have made course corrections earlier. I would have been less married to the technological concept. I now believe that it will never be attained, and that formal verification will only complement simulation, not replace it. Static applications provide a lot of value, but they are only part of the solution. EE Times : Designs these days are based on IP blocks that combine existing content with a small amount of new content. Does this change your strategy going forward? Narain : There is an evolution in the methodology. As I mentioned , the value of an engineer is in bridging the gap between what we have and what is to be attained. In the past few years, the size of designs has doubled, and this will happen again. There has been improved resolution in the verification characterisation problem. I call these the known unknowns—things such as the CDC problem, cache coherency problems. If solutions are known, static solutions are always superior to dynamic solutions, and there is a new set of static solutions that is emerging, and we are targeting a set of those. Then there are the unknown unknowns, where simulation still plays an important role. The increasing complexity has created new failure modes, such as needing multiple clock domains, so new opportunities are always arising, and static tools are capable of solving some of these. EE Times : What is the next chapter? Narain : Right now, it is about completing the endeavors we have picked up. We are making some new bets, and hopefully this time with better wisdom, but the focus is on execution. For the future, opportunities come, but you don't know when. Right now, I am focused on the challenges in front of me. EE Times : Do you ever regret having gone into EDA? Narain : No. Hindsight is always 20/20, but you have to take responsibility for making the decisions and accepting them. I have learned not to be married to anything—well, I am married to my wife and very committed there. Water flows and finds its own level, and I have learned to change my thinking based on new information. In the final part of this CEO profile, Narain talks about the larger challenges and opportunities facing the EDA industry. Readers, how many people are now using formal technology in some way to solve their verification challenges, and what other problems do you wish formal verification could solve? Brian Bailey EE Times  

关于 Kinetis L series 的 block diagram 的微词   有多少像我一样的童鞋, 在学习一门新的 uController 时, 郑重而期待地寻找 datasheet 中最基本的系统框图, 也就是 block diagram 来进行了解?   有多少像我一样的童鞋, 在观赏了 Kinetis L 系列 datasheet 的系统框图时, 脸上的表情: 热情 - 期待 - 不解 - 惶然 - 冷漠 - 不屑, 就跟川剧变脸一样啦~~   我们工程师等待的, 不是并行列表, 也不是内容积木, 我们工程师等待的是一顿营养大餐, 由 core - bus - modules - osc - inteface 编织而成的, 布满箭头和走线的, 清晰表达模块交互的, 几乎能从 2D 表格中表现并帮助在脑海中描画出,  一份 3D 的, 关系纠缠的, 思维活跃的系统框图, 可是 Freescale 的 reference document, 好嘛, 我们找遍了, fact sheet, product berif, data sheet, reference manual, peripheral module quickreference, 好嘛, 我们只得到这个:     作为比较, 我给出 NXP LPC2xxx 的这个:   作为具有中国特色的工程师的惯常表达方式,   我想给出这个!     另外还有这个...     烦恼的 Allen 作于深圳福田 而且是周六傍晚加班中~~~