原创 Time Borrowing in Latch-based Designs (copied)

 2009-7-31 14:22  4357 6 6 分类: FPGA/CPLD

Copied from "design compiler technology background"

You can leverage Design Compiler’s unique technique, time borrowing, to optimize near-critical paths and reduce delay costs in latch-based designs. A latch is a simple, 1-bit level sensitive memory device. Design Compiler allows borrowing time from next clock cycle to extend the time during which latch is enabled if the path leading to the data pin of a latch is too long. For example, in the following two-stage latch based design, the combinational logic block between Latch1 and Latch2 may have more delay than the delay between Latch2 and Latch3. To resolve this discrepancy, the first stage can borrow time from the second clock cycle. In this event, the second clock cycle is left with less time to accommodate the combinational logic block between Latch2 and Latch3.