原创 design compiler 学习记录

这是最近在看dc相关的user guide 还有一些资料所做的记录，以便日后查找和温习。

1,Design Compiler uses technology libraries, synthetic or
DesignWare libraries, and symbol libraries to implement
synthesis and to display synthesis results graphically.
During the synthesis process, Design Compiler translates the
HDL description to components extracted from the generic
technology (GTECH) library and DesignWare library. The
GTECH library consists of basic logic gates and flip-flops. The
DesignWare library contains more complex cells such as adders
and comparators. Both the GTECH and DesignWare libraries are
technology independent, that is, they are not mapped to a
specific technology library. Design Compiler uses the symbol
library to generate the design schematic.

2,XG mode uses optimized memory management techniques that
increase the tool capacity and can reduce runtime. In XG mode, you
use the dctcl command language to interact with Design Compiler.
The Design Compiler documentation set describes the default XG
mode.
3,The two basic compile strategies that you can use to optimize
hierarchical designs are referred to as top down and bottom up.
In the top-down strategy, the top-level design and all its subdesigns
are compiled together.
In the bottom-up strategy, individual subdesigns are constrained and
compiled separately. After successful compilation, the designs are
assigned the dont_touch attribute to prevent further changes to
them during subsequent compile phases. Then the compiled
subdesigns are assembled to compose the designs of the next
higher level of the hierarchy (any higher-level design can also
incorporate unmapped logic), and these designs are compiled.

4,For designs that have significantly tight timing constraints, you can
invoke a single DC Ultra command, compile_ultra, for better
quality of results (QoR).
5,When you specify the files in the link_library variable, consider
that Design Compiler searches these files from left to right when it
resolves references, and it stops searching when it finds a reference.
If you specify the link library as {"*" lsi_10k.db}, the designs in
memory are searched before the lsi_10k library.

5,When performing timing analysis, Design Compiler must consider
the worst-case and best-case scenarios for the expected variations
in the process, temperature, and voltage factors.

6,Use the set_drive or set_input_transition command to set
the drive resistance on the top-level ports of the design when the
input port drive capability cannot be characterized with a cell in the
technology library.
7,This information
helps Design Compiler select the appropriate cell drive strength of
an output pad and helps model the transition delay on input pads.

8,cell的delay都由input transition 和 output load查表得到，如果input transition
和 output load比较大，在表的范围外，查表结果误差比较大，delay计算不准确，所以生
产出的芯片可能无法正常工作。所以set_max_transition 和 set_max_capcitance的作用类似。
一般为0.12/f左右

9,不涉及综合的策略，

1.设计规则约束（隐含约束）[高优先级]
 由工艺库定义的，保证最终电路可以正常工作，必须遵守。

 最大翻转时间：set_max_transition
 扇出:set_max_fanout
 电容：set_max_capacitance

 最小电容:set_max_capacitance

2.设计优化约束（显示约束）
 用户定义的，DC根据这些进行综合的优化。前提是不能违反设计规则约束。
 优化约束:
  面积    时间
    set_max_area  creat_clock  set_max_delay
    set_input_delay  set_min_delay
    set_output_delay
-----------------------------------------------------------------------------------------------

1.翻转时间
 一个网络的翻转时间是指它的驱动源改变逻辑值所需要的时间。它是基于工艺库中的数据得到的。
 对于非线性时延模型，输出的翻转时间是输入翻转时间和输出负载的函数。
 若要改变，则DC会尝试满足。
 例如，把adder中的所有网络设置3.2的最大翻转时间：
 dc_shell>set_max_transition 3.2 find(design,adder)
2.扇出负载
 一个网络的最大扇出负载就是这个网络能够驱动的负载的数量。
 DC中，给一个输入端口设置扇出的限制，使用fanout_load属性，对于输出，使用max_fanout属性。
 一个输出端口扇出负载为10，可以驱动10个扇出负载为1的输入管脚。
 输入端口扇出负载不一定为1，可以大于1.
 例如，设置adder的所有网格设置了最大扇出负载值为16.
 dc_shell>set_max_fanout 16 find(design,adder)
3.电容（Capacitance）
 翻转时间的约束并没有直接控制网络的电容值。
 若需要，在DC中可以使用set_max_capacitance设置最大电容的约束。
 对于一个输出端口，DC将它相连的网络及端口的电容值相加，再把这个电容值和输出端口的max_capacitance比较，判断是否满足约束
 例如，设置所有网络最大电容值为3
 dc_shell>set_max_capacitance 3 find(design,adder)
 
 set_load
 set_fanout_load
 set_drive
 set_driving_cell
 
 set_max_transition
 set_max_fanout
 set_max_capacitance
 
 10,Skew的定义就是最长路径减去最短路径的值。
 
 11,The elaborate command does the following:
? Translates the design into a technology-independent design
(GTECH) from the intermediate files produced during analysis
? Allows changing of parameter values defined in the source code
? Allows VHDL architecture selection
? Replaces the HDL arithmetic operators in the code with
DesignWare components
? Automatically executes the link command, which resolves
design references

11,用set_critical_range命令定义关键路径的优化范围，难道是大于这个的就优化？？？
12,set_structure用来控制优化的

13,Some layout tools have difficulty reading the netlist that contains tri wires,
tran primitives and assign statements. These are Verilog specific primitives
and statements that are generated in the netlist for many possible reasons.
DC generates tri wires for designs containing “inout” type ports. For designs
containing these types of ports, DC needs to assign values to the bidirectional
port, thus producing tri wire statement and tran primitives. To
prevent DC from generating these, users may use the following IO variable
in the setup file. When set to true, all tri-state nets are declared as wire
instead of tri.

14,set_multiple_port_nets解决一跟线驱动多个输出port的问题

15,ungroup removes a level of hierarchey

16,要求多个时钟之间的周期必须有一个最小公倍数，这样的话，在一个最小公倍数周期内，两个clock是重复的。

17，To undo a set_false_path command, use the reset_path
command with similar options.

18,\ Indicates a continuation of a command line.

19,Command names and variable names are case-
names, design object names, and strings.大小写敏感。

20，Disable the printing of one or more messages. suppress_message

21，If you run dc_shell scripts overnight to compile a design, you cannot see warnings or error
messages echoed to the command window while your scripts are running. You can direct the
output of a command, procedure, or script to a specified file in two ways:
? By using the traditional UNIX redirection operators (> and >>)
? By using the redirect command

22,Use the printvar command to display all of the variables defined in your current session,
as well as their values.

23,Variable groups organize variables that perform similar functions. Most predefined variables
are part of a group, such as the system variable group or the plot variable group.

24,

Command                    Object
set_max_fanout             Input ports or designs
set_max_capacitance        Input ports or designs
set_fanout_load            Output ports
set_load                   Ports or nets
set_max_transition         Ports or designs
set_cell_degradation       Input ports
set_min_capacitance        Input ports

25,The following script guides Design Compiler to optimize for area only. It constrains a design
only for minimum area (when you do not care about timing). For the timing to make sense,
you must apply clocking and input and output delay.
/* example script for smallest design */
remove_constraint -all
remove_clock -all
set_max_area 0

26,It is important to understand that port isolation can be applied only to the input or output ports
of the current design.Port isolation is currently intended for use only during bottom-up compilation. That is,
isolating hierarchical instance pins of lower- level designs from the top-level design in a
top-down compilation is not supported.

27,The hold multiplier 1 signifies that the next active edge plus 1 at the path startpoint is
checked against the same active edge at the path endpoint.

28,The -hold option of the set_multicycle_path command
launches the hold data at the edge before or after the default edge,
but Design Compiler still checks the hold data at the edge used for
checking setup.

29,constraints includes design rule constraints and design optimization constraints.

30, read_lib ./xxx.lib
    report_lib xxx
   
    or
   
    read_file ./xxx.db
    report_lib xxx
通过命令report_lib可以看lib的很多信息。

31,The description of clock edges for one period. A simple waveform has two edges — for
example, {0.0 5.0}.  两个数字分别是两个延的位置。

32,Design Compiler uses technology libraries, synthetic or
DesignWare libraries, and symbol libraries to implement
synthesis and to display synthesis results graphically.
During the synthesis process, Design Compiler translates the
HDL description to components extracted from the generic
technology (GTECH) library and DesignWare library. The
GTECH library consists of basic logic gates and flip-flops. The
DesignWare library contains more complex cells such as adders
and comparators. Both the GTECH and DesignWare libraries are
technology independent, that is, they are not mapped to a
specific technology library. Design Compiler uses the symbol
library to generate the design schematic.

33,
Library type          Variable                  Default File    extension

DesignWare library    synthetic_library         {}              .sldb

designware只不过是库的类型，而synthetic_library是系统变量。

DesignWare Library (DesignWare库)
    DesignWare Library包含了最常用的结构以外的IP，这对于设计开发ASIC和SOC来讲是必要的。当超过2万5仟名设计人员使用Design Ware库的时候，您可以相信这里所有开发的IP是具有最高质量的，且易于使用。当一个特许权交给设计人员时，就意味着他可以存取库中的全部可综合的和经过验证的IP。

    Design Ware库包含了基本的可综合的构建块，这对于设计一个芯片是必需的。数据通路单元例如高度优化的加法器和乘法器，它们是DesignWare库中首要的元件，而且Synopsys公司在电路设计的时序和面积等方面进行了大量的改进。去年以来Design Ware库经过了扩充，现在该库已包含了大量的功能块，包括存储器、控制器、存储器BIST（内建自测试）解决方案、AMBA片上总线解决方案、DesignWare Star IP微处理器核等等，组成了完善的Design Ware验证库。

1 改善了设计的综合质量
2 提供许多SOC设计必需的IP模块
3片上总线（AMBA）
4外围
5存储器控制器
6构建块
7验证IP
8低的设计风险

34，Design Compiler has a built-in static timing analyzer
called DesignTime.

35，
pre_layout
create_clock -p 30 -n MCLK Clk
set_clock_uncertainty 0.6 MCLK
set_clock_latency -source 4 MCLK
set_clock_latency 2 MCLK

post_layout
create_clock -p 30 -n MCLK Clk
set_clock_latency -source 4 MCLK
set_propagated_clock MCLK

36,How do I create a virtual clock?
A: It is the same as defining a clock, but
do not specify a clock pin or port:
l You must name your virtual clock, since there is
no clock port for the virtual clock

37,set_false_path主要用在两个地方:Useful for:Constraining asynchronous paths,Constraining logically false paths

38，Entire design will be returned
to a GTECH representation:
Logic-level optimization will be performed
Gate-level optimization will be performed
DesignWare Implementations may still be changed

A successive compile will
probably not help, unless you
change something:
 Modify the constraints
 Change the set_structure or set_flatten options
 Change the map effort of compile
 
 
compile -incremental_mapping
Only gate-level optimization is done:
The design is not taken back to “GTECH”
No logic-level optimization
DesignWare Implementations may still be changed
Incremental is much faster than regular compile

39，set_critical_range 2 [current_design]
This command causes DC to optimize all violating paths within 2ns of the critical path

Very CPU and memory intensive Use with caution!

难道应该是：优化关键路径，这个关键路径的在2ns的范围内，也就是比max delay只小2ns？？
是这样：这个在optimization阶段作用，先map，开始计算timing，有违反的，有不违反的，违反的在这个范围内就可以进行优化了，
那么不在这个范围内又违反的，进行cell替换？？

是这样？？先找出最大的citical 路径，比如说是15，如果默认的话就只有话15这条路径，如果 set_critical_range 2 current_design

那么15，13的都要优化？？？

When you add a critical range to a path group, you change
the maximum delay cost function from worst negative slack to critical negative slack. Design
Compiler optimizes all paths within the critical range.
A guideline for the maximum critical range value is 10 percent of the clock
period.

40，The first phase of compile maps all blocks to gates without
regard to constraints.

During the second phase, Design Compiler:
l Optimizes logic to meet timing and area constraints
l Fixes violations caused by the surrounding blocks

41，Experimenting with speed and area to get the smallest or fastest design is called exploring
the design space.

42，During mapping, Design Compiler selects components from the technology library to
implement the logic structure. Design Compiler tries different logic combinations, using only
components that approach the defined speed and area goals.

43,Some layout tools have difficulty reading the netlist that contains tri wires,
tran primitives and assign statements. These are Verilog specific primitives
and statements that are generated in the netlist for many possible reasons.

When set to true, all tri-state nets are declared as wire
instead of tri. set verilogout_no_tri true

在dc生成的网表中已经没有assign这些东西了，全是库中的cell来构建的一个网表。

44，Remove Unconnected Ports

Because a design may contain many such unconnected ports, it is possible that a real warning
may get lost between the numerous unconnected ports warnings.

45，For example, a D flip-flop containing 4 ports
namely, D, CLK, Q and QN, may be connected as follows:
DFF dff_reg (.D(data), .CLK(clock), .Q(data_out) ) ;
In the above case, DC does not write out QN the port, since the function of
the inverting QN output is not utilized in the design.

Setting the value of the
following variable to true in the setup file can prevent this mismatch:
set verilogout_show_unconnected_pins true

46，the ungroup command removes the hierarchy in the design (netlist) and make it flat..
flattening doesnt mean removing hierarchy，仅仅是一个用来优化的选项。

ungroup is to remove hierarchy !!

The group and ungroup commands provide the designer with the capability
of altering the partitions in DC, after the design hierarchy has already been
defined by the previously written HDL code.

The group command combines the specified instances into a separate block.

ungroup   仅仅是将当前设计下的层次去掉，比如top 包含u_add ,而u_add又包含了sub，
current_design top
那么采用ungroup -all，则会将u_add这一层次去掉，而sub这个层次还存在，

如果使用 ungroup -all -flatten，则将全部的层次打平。

47，Boundary Optimization. Direct Design Compiler to perform optimization across
hierarchical boundaries (boundary optimization) by using one of the following commands:
dc_shell> compile -boundary_optimization
or
dc_shell> set_boundary_optimization subdesign

48，set_fix_multiple_port_nets -feedthrough   用来隔离输入输出port的
    set_fix_multiple_port_nets -all -buffer_constants解决常量的。
   
feedthrough 就是指输入直接连接到输出