原创 VHDL范例1---- 全加器的几种实现方法

一、1位全加器

ENTITY full_add IS

    PORT( a,b,cin : IN BIT;

                cout,sum: OUT BIT );

END full_add;

ARCHITECTURE adder OF full_add IS   --逻辑表达式实现

BEGIN

    cout <= ( (a xor b) and cin ) or ( a and b );

    sum <= ( a xor b ) xor cin;

END adder;

ARCHITECTURE adder2 OF full_add IS   --真值表实现

SIGNAL abcin :BIT_VECTOR( 0 to 2 );

SIGNAL yout : BIT_VECTOR( 0 to 1 );

BEGIN

    abcin <= a & b & cin;

    WITH  abcin SELECT

        yout <= "00" WHEN "000",
  
         "01" WHEN "001",
  
         "01" WHEN "010",
  
         "10" WHEN "011",
  
         "01" WHEN "100",
  
         "10" WHEN "101",
  
         "10" WHEN "110",
  
         "11" WHEN "111";
    cout <= yout( 0 );
    sum <= yout( 1 );

END adder2;

二、4位加法器

之前已生成了full_add.vhd

ENTITY add4par IS

    PORT( c0: IN BIT;

                a,b: IN BIT_VECTOR( 4 downto 1 );

                c4: OUT BIT;

                sum: OUT BIT_VECTOR( 4 downto 1 ) );

END add4par;

ARCHITECTURE adder of add4par IS

    COMPONENT full_add

         PORT( a,b,cin: IN BIT;

                     cout,sum: OUT BIT);

    END COMPONENT;

    SIGNAL c: BIT_VECTOR( 3 downto 1 );

BEGIN

    adder1:full_add PORT MAP( a => a(1),b=>b(1),cin=>c0,cout=>c(1),sum=>sum(1) );

    --上面的书写方式中，参数顺序可任意调整。

  adder2: full_add PORTMAP( a(2),b(2),c(1),c(2),sum(2) );

  adder3: full_add PORTMAP( a(3),b(3),c(2),c(3),sum(3) );

  adder4: full_add PORTMAP( a(4),b(4),c(3),c(4),sum(4) );

END adder;

--利用生成语句，可进一下简化语句的书写

ENTITY add4gen IS

     PORT( c0: IN BIT;

                a,b: IN BIT_VECTOR( 4 downto 1 );   -- 4改为8

                c4: OUT BIT;

                sum: OUT BIT_VECTOR( 4 downto 1 ) );   -- 4改为8

END add4gen;       

ARCHITECTURE adder OF add4gen IS

    COMPONENT full_add

          PORT( a,b,cin:IN BIT;

                      cout,sum: OUT BIT );

     END COMPONENT;

    SIGNAL c: BIT_VECTOR( 4 downto 0 );  -- 4改为8

BEGIN

    c(0) <=c0;

    adders:

                FOR i IN 1 to 4 GENERATE   --FOR i IN 1 to 8 GENERATE

                             adder: full_add PORTMAP(a(i),b(i),c(i-1),c(i),sum(i) );

                 END GENERATE;

      c4 <= c(4);   --c8<=c(8)

END adder;

若要扩展为8位加法器，则很容易修改，将上面的4改为8即可