原创 CYPRESS CY7C68013A（FX2LP系列）开发手记——Cypress KB集锦(2)(

FX2芯片是否可以使用ezusb.sys驱动程序
可以的。 ezusb.sys可以用于EZ-USB和EZ-USB FX。但是，我们建议对FX2和FX2LP芯片使用最新的驱动程序CyUSB.sys。下载并安装SuiteUSB SDK 3.4.2之后，CyUSB.sys位于 C:\Program Files\Cypress\Cypress Suite USB 3.4.2\Driver 目录下。

 

我们计划在基于FX2LP的设计中在USB线上增加ESD二极管，这样可以吗？

在USB线上增加ESD二极管等器件(choke, ESD diode, switch etc)，将增加线的电阻和电容，我们是不建议这样做的。

Here are the parameters that the device is expected to meet as per spec, D+ and D- should have 45 ohm +/- 10% to ground and a differential impedance of 90 ohm +/- 10% between them.For capacitance, in high speed
Capacitance to Ground on each line:CHSLOAD≤ 10 pF
Matching of Capacitances to Ground:≤ 1.0 pF
The differential capacitance across the transceiver inputs should be no more than 5.0 pF.
For full-speed due to change in termination it will be 100pF +/- 10% (measured at B-receptacle).
It would be a good idea to check with your PCB manufacturer if the board can be fabricated to meet these values even with the addition of the ESD diode before incorporating them in the design.

 

 

What is the usage of In-Bulk-NAK (IBN) Interrupt in FX2LP?

When the host requests an IN packet from an EZ-USB BULK endpoint, the endpoint NAKs (returns the NAK PID) until the endpoint buffer is filled with data and armed for transfer, at which point the EZ-USB answers the IN request with data.Until the endpoint is armed, a flood of IN-NAKs can tie up bus bandwidth.Therefore, if the IN endpoints are not always kept full and armed, it may be useful to know when the host is ‘knocking at the door’, requesting IN data.The IN-BULK-NAK (IBN) interrupt provides this notification.The IBN interrupt fires whenever a Bulk endpoint NAKs an IN request.Instead of putting the data in the IN Endpoint and keeping it armed all the time, FX2LP can identify the IN endpoint on which data was requested by the host on getting an IBN interrupt, place data on it and then arm the endpoint.The IBNIE/IBNIRQ registers contain individual enable and request bits per endpoint, and the NAKIE/NAKIRQ registers each contain a single bit, IBN, that is the OR’d combination of the individual bits in IBNIE/IBNIRQ registers.For further information on using this interrupt refer IN-BULK-NAK interrupt in FX1/FX2LP example project

 

Does FX2 and FX2LP support streaming data transfer?

Yes. Please refer to the application note Streaming data through Bulk/Isochronous Endpoints of the EZ-USB FX2 and FX2LP AN4053 which you may download from the following link from the Cypress website. http://www.cypress.com/?rID=12967

 

Build errors with SuiteUSB example projects

Question :The firmware example projects with SuiteUSB 3.4.2 build with errors, even though the projects are built as is.Why? Response :The firmware projects with SuiteUSB 3.4.2 access various header and library files from the path ,where development kit CY3684 is installed.In case, if CY3684 is not installed on your system, the projects are bound to throw errors, as they are unable to access the appropriate files from the expected path.To resolve this, please install CY3684 .

 

 

 

Detecting NAKing of OUT transfers by FX2LP 最近更新：2010 年 10 月 01 日

Question:How can i detect in firmware when an OUT transfer has been NAKed by FX2LP due to lack of space in the FIFOs? Response:High-speed USB implements a PING-NAK mechanism for (Bulk and Control) OUT transfers.When the host wishes to send OUT data to an end-point,  and it was previous data transfer was responded by a NYET, it first sends a PING token to see if the endpoint is ready (for example, if it has an empty buffer).If a buffer is not available, the FX2LP returns a NAK handshake.PING-NAK transactions continue to occur until an OUT buffer is available, at which time the FX2LP answers a PING with an ACK handshake and the host sends the OUT data to the endpoint. FX2LP implements PING-NAK interrupt as EP0PING, EP1PING and so on, one for each endpoint.The EPxPING interrupt is asserted when the host PINGs an OUT endpoint and the FX2LP responds with a NAK because the particular endpoint buffer memory is not available. This interrupt can be used to detect when an OUT transfer has been NAKed by FX2LP due to lack of space in the FIFOs.For further information on using this interrupt refer PING-NAK interrupt in FX1/FX2LP example project

 

 

 

USB to Parallel Converter Using FX2LP 最近更新：2010 年 09 月 22 日

Question:How can I use FX2LP to make an usb to parallel converter? The data received over the USB should be made available on a parallel data bus on the GPIO pins. Response:There are two methods to implement a USB to Parallel interface in FX2LP.  The GPIF or Slave FIFO mode of FX2LP can be used depending on the external device which is being interfaced with FX2LP. Without using the GPIF or Slave FIFO interface, firmware can be written to implement the same using the 8051 core.

 

 

Firmware Download through CyConsole or Control Centre 最近更新：2010 年 08 月 30 日

Question :It is observed everytime that when a hex file or a .iic file is getting downloaded by the CyConsole or the Control Centre, some hex data is being written into the chip before the correct hex file is written.What is the explanation for this procedure? Answer :It is the Vend_Ax.hex file which is hardcoded into the cyconsole application and is written into the onchip ram everytime you download a hex file or a .iic file.This is needed because if the hex file that we are downloading contains address locations of size beyond that of our onchip ram, cyconsole will write that packet of data into the external ram using the 'a3' vendor command.The FX2LP core will recognize the 'a3' vendor command only due to the reason that it is now executing the code that was present in Vend_Ax.hex. After writing all the bytes of code which had addresses in external ram, cyconsole will reset the cpu and download the rest of the code bytes onto the on-chip ram using the a0 vendor command which is hardcoded into fx2lp and which doesnot need the Vend_Ax code to support it.

 

  
EP1 Buffer Reset

最近更新：10/05/2009
Question:Is it possible to reset the EP1 buffers the same way as with the other EP buffers (2,4,6 and 8)?

Response:Unlike the other endpoint buffers, that is, EP2,4,6,8 buffers, which can be reset by the FIFORESET register, the only way to reset an EP1 buffer is by a hard reset.A USB Bus Reset or a CPU reset does not reset the EP1 buffer.

 
FIFO byte count registers

最近更新：11/30/2009

Question:Explain the count value present in EPXFIFOBCH, EPXFIFOBCL registers.

Response:The EPXFIFOBCH, EPXFIFOBCL registers keeps count of the number of bytes in the concerned endpoint received from the peripheral side.So, this register will not reflect bytes sourced by the 8051 CPU or bytes received from the host.The count only reflects the number of bytes in the endpoint as a consequence of that endpoint being under the control of the peripheral domain.

用于 FX2LP 枚举的固件

Question:Does FX2LP do all the enumeration by itself or user has to do programming?

Response:FX2LP is a general purpose High Speed USB peripheral controller.So user has to write code according to the purpose.We provide the frameworks (pre-written code) which can do enumeration by itself with no extra effort on programming from the customer side.The frameworks can be found in the path C:\Cypress\USB\Target\Fw\LP after you download and install SETUP_FX2LP_DVK_1004.exe from the link

CY3684 EZ-USB FX2LP Development Kit in the default path.You can also find the examples under C:\Cypress\USB\Examples\FX2LP which is based on this framework.To start with you can refer EZ-USB_GettingStarted.pdf and Dvk _Users _Guide.pdf in the same link  CY3684 EZ-USB FX2LP Development Kit.

Bypass Capacitor Requirements For FX2LP

最近更新：12/16/2009

 
Question:Are there any design guidelines for selecting the bypass capacitors required by CY7C68013A?

Answer :Decoupling capacitors should be ceramic type of a stable dielectric.For lower value capacitance, it is appropriate to use Class 1 dielectric capacitors, C0G (also referred to as NPO).Class 2 X7R should be used for the larger values.It is
recommended that 0.01-μF and 0.001-μF capacitors be used to decouple supply pins nearest the pair of USB transceiver circuits.The 0.001-μF should be C0G dielectric.This will help decouple the power supply at the frequency range of highspeed USB switching.The other power supply pins should be decoupled with 0.1-μF X7R capacitors.It is important to have short trace runs for the power and ground connections from the EZ-USB FX2 component to solid power and ground planes.

The specific recommendation for the ceramic capacitor nearest each EZ-USB FX2 power pin is shown in the table below:

QFN PIN NUMBER CAPACITOR VALUE QFN PIN NUMBER CAPACITOR VALUE
7 .01 uF 43 .1 uF
11 .001 uF 55 .1 uF
17 .1 uF 3 .1 uF
27 .1 uF 3 .22 uF
32 .1 uF    

ESD protection for FX2LP

最近更新：12/16/2009

Question:Does FX2LP have ESD protection?

Response: The FX2LP has ESD protection up to 2KV.This information is available on section 6 of the FX2LP datasheet.
If you want to achieve higher protection then you can refer to the USB-IF website. The Page 10 of the document High Speed USB Platform Design Guidelines in the link http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf. will provide the relevant information on increasing the ESD protection.

Multiple FX2LP Devices Connected to Host

最近更新：12/30/2009
Question: How can host distinguish between and communicate with multiple FX2LP devices connected to if each of the devices have the same VID/PID?

Answer :The iSerialNumber byte in the DeviceDescriptor can be used to uniquely identify the devices even if the devices have the same VID/PID. 

How to Detect in Firmware if the Device has Enumerated as a High Speed or Full Speed Device

最近更新：12/30/2009 
Question:How can it be detected in firmware whether a device has enumerated as a full speed device or a high speed device?

Answer:The register USBCS in FX2LP contains a bit HSM(USBC.7) which is set high when enumeration happens in high speed.Also, the 0-1 transition of this bit will cause an HSGRANT interrupt request.
 
Problems Faced When cyusb.sys is Used in a Multi Core Host Enviroment

最近更新：01/04/2010
Question:Problems Faced When cyusb.sys is Used in a Multi Core Host Enviroment.

Answer:There are known perfomance issues for cyusb.sys when it is used with a multi core host.The issues are related to occasional delays occuring in between transactions. The same has been declared in the release note of CySuiteUSB3.4.1 which can be found at C:\Program Files\Cypress\Cypress Suite USB 3.4.1 (after installing the CySuiteUSB 3.4.1 Software Development Kit).
 
FX2LP not enumerating for firmware (code+xdata) of size greater than 16 K

最近更新：01/04/2010

Question :  FX2LP does not enumerate when firmware (code+xdata) of size greater than 16 K is downloaded.Why is this happening?

Answer:Check in your .m51 file where the compiler is placing the descriptor files.The issue might be that the compiler is putting the descriptor table into external memory.When this happens fw.c relocates the descriptor table to memory location 0x0080 where it overwrites some portion of the code.This might cause error in enumeration or incorrect functioning of some part of code.You can specify the starting location of your code memory after leaving space for the interrupt vector tables and the descriptor table.

For example, in the BL51 locate tab, you can specify your code to begin at a location greater than (0x0080 + length of your descriptor table).Here, 0x0000 - 0x0080 will contain the interrupt vector table.For example if the length of your descriptor table is 80h,  you can safely start your code from 0x120h.

 
Windows 7 Version of CyUSB.sys

最近更新：01/04/2010 
Question:Does Cypress provide a Windows 7 Version of CyUSB.sys?

Answer:The Vista compatible version of CyUSB.sys has been tested compatible with Windows 7 as well.You can use the same driver files for Windows 7.

WinCE Version For CyUSB.sys

最近更新：01/04/2010 
Question:Does Cypress provide a version of CyUSB.sys that is compatible with the WinCE OS?

Answer:We currently do not have a Windows CE version for CyUSB.sys . Please contact our Cypress certified consultants, Cypros who will be able to help you with your driver development.We also recommend Jungo, a third party driver developer, to customers whose designs require development of a custom driver.

I2C Clock Stretching in FX2LP

最近更新：01/04/2010
Question:Does the I2C controller of FX2LP support clock stretching?

Answer:The FX2LP I2C controller supports clock stretching.Once the master(FX2LP) drives SCL low, external slave devices can hold SCL low to extend clock-cycle times.

Plug n Play Detection when using CYAPI.lib

最近更新：08/30/2010
Question :How can we implement hot-plugging detection when using cyapi.lib?

Answer :You can use the constructor for the CCyUSBDevice class to register for PnP events.

Here is an example,

void __fastcall TMainForm::FormCreate(TObject *Sender)
{
USBDevice = new CCyUSBDevice(Handle);
CurrentEndPt = USBDevice->ControlEndPt;
}
// Overload MainForm's WndProc method to watch for PnP messages
// Requires #include
void __fastcall TMainForm::WndProc(TMessage &Message)
{
if (Message.Msg == WM_DEVICECHANGE) {
// Tracks DBT_DEVICEARRIVAL followed by DBT_DEVNODES_CHANGED
if (Message.WParam == DBT_DEVICEARRIVAL) {
bPnP_Arrival = true;
bPnP_DevNodeChange = false;
}

// Tracks DBT_DEVNODES_CHANGED followed by DBT_DEVICEREMOVECOMPLETE

if (Message.WParam == DBT_DEVNODES_CHANGED) {
bPnP_DevNodeChange = true;
bPnP_Removal = false;
}
if (Message.WParam == DBT_DEVICEREMOVECOMPLETE) {
bPnP_Removal = true;
PDEV_BROADCAST_HDR bcastHdr = (PDEV_BROADCAST_HDR) Message.LParam;
if (bcastHdr->dbch_devicetype == DBT_DEVTYP_HANDLE) {
PDEV_BROADCAST_HANDLE pDev = (PDEV_BROADCAST_HANDLE) Message.LParam;
if (pDev->dbch_handle == USBDevice->DeviceHandle())
USBDevice->Close();

}

}

// If DBT_DEVNODES_CHANGED followed by DBT_DEVICEREMOVECOMPLETE

if (bPnP_Removal && bPnP_DevNodeChange) {
Sleep(10);
DisplayDevices();
bPnP_Removal = false;
bPnP_DevNodeChange = false;
}

 

// If DBT_DEVICEARRIVAL followed by DBT_DEVNODES_CHANGED

if (bPnP_DevNodeChange && bPnP_Arrival) {
DisplayDevices();
bPnP_Arrival = false;
bPnP_DevNodeChange = false;
}

}
TForm::WndProc(Message);
}

To more about this implementation please go through the attached CYAPI programmer's reference.

I2C speed 
Question: In FX2LP’s I2C interface, when we select 400 kHz, we only get ~300 kHz bus speed.Similarly when we select 100 kHz, we get ~85 kHz.What is the reason?

Response:The FX2LP’s I2C is configured such that it does not exceed the maximum speed for that mode when there is a variation in the input clock of the IC and other parameters.Normally in 100 KHz mode the clock runs just over 90 KHz and in 400 KHz mode the clock runs around 360 KHz.

INT Line Behavior

最近更新：08/30/2010
问题:What happens if an interrupt from any other source occurs after the read register command has been issued and before the data is available on FD [7:0]?

Response:The INT line is solely dedicated to the read register after the read register command is issued by the external master.The read register sequence occurs in 3 steps

<!--[if !supportLists]-->1.   External master issues a read register command by providing the register address to be read.<!--[endif]-->

<!--[if !supportLists]-->2.   SX2 puts the data from the corresponding register on FD[7:0]<!--[endif]-->

<!--[if !supportLists]-->3.   SX2 asserts INT# pin to inform the external master that data is available on FD [7:0]<!--[endif]-->

If an interrupt from any other source occurs after step1 and before step3 of the read register sequence, the SX2 will buffer that interrupt until the read request completes and the external master has read the data.This insures that after a read sequence has begun, the next interrupt that is received from the SX2 will indicate that the corresponding data is available.The other interrupt source gets buffered and will not interfere with read request.After reading the register data, the processor will be notified of the interrupt source via the INT line going low again.

Configure the ports PA, PB, PC, PD and PE of FX2LP as General-Purpose I/O

最近更新：08/19/2010
Question:How to configure the ports PA, PB, PC, PD and PE of FX2LP as general-purpose I/O?

Response:The EZ-USB FX2LP (CY7C68013A) has up to five eight-pin bidirectional I/O ports Px[0..7], where x is the port (A, B, C, D, or E).When using Ports mode, the bit 0 and 1 of the IFCONFIG register has to be configured to “0”.In Ports mode, all the IO pins are general-purpose I/O ports. The registers which are important to control and configure the IO ports are the OEx , IOx and the PORTxCFG.Here, x can be A,B,C,D,and E.

An OEx register (where x is A, B, C, D, or E), which sets the input/output direction of each of the 8 pins (0 = input, 1 = output).
An IOx register (where x is A, B, C, D, or E).Values written to IOx appear on the pins which are configured as outputs; values read from IOx indicate the states of the 8 pins, regardless of input/output configuration.
 
Example 1, set IOB to toggle PB0 pin which can be observed using one LED.
  IFCONFIG = 0x00;     // set the ports as general-purpose I/O
  OEB |= 0xFF;           // set PORT B as outputs
  IOB |= 0x01;            // set PB0 high
  EZUSB_Delay(2000); // delay for ~2000 ms
  IOB &= 0x00;           // set PB0 low
 
Example 2, set PA0 pin as high output.
  IFCONFIG = 0x00;     // set the ports as general-purpose I/O
PORTACFG &= 0x00; // set the bit0 of PORTACFG register to “0” as GPIO
  OEA |= 0x01;          // set PA0 as output
  IOA |= 0x01;          // set PA0 high
 
 
The PORTxCFG register selects alternate functions for the I/O pins.Most I/O pins have alternate functions which may be selected using Ports configuration registers (see Table 13-1 through Table 13-9 in the EZ-USB Technical Reference Manual).For more details about the I/O pins of FX2LP, please review the chapter 13 of EZ-USB Technical Reference Manual.

CYAPI - Detect if some other application is using the USB device

最近更新：08/18/2010
Question:How do I detect using the CYAPI library, if some other application is already using my USB device?

Answer :The IsOpen() method can be used to check the same.This method is a member of the CCyUSBDevice class.The IsOpen( ) method returns true if CCyUSBDevice object already has a valid handle to a device attached to the CyUSB driver.

For example:

if(USBDevice -> IsOpen())
{
// The device is open and is being used by another application
// This condition is also true if the current application has opened the device and has a handle
}

CCyUSBDevice->DeviceName() Not Returning the String from Device Descriptor in Vista

最近更新：08/12/2010 
Question :While working with the CYAPI.lib and cyusb.sys driver  in Vista  the function
CCyUSBDevice->DeviceName() returns something similar to Port_#0001.Hub_#0001 and not the string from the device descriptor.This is also visible in cyconsole.

Response :This is a known issue with CYAPI.lib. CyConsole will show Port and Hub address in the place of Device Name in Vista 32 and 64 bit OS. You can use USBDevice->Product instead of USBDevice->DeviceName.This will return the same value on all operating systems.
 
Downloading Firmware without an EEPROM to FX2LP

最近更新：08/12/2010
Question:How can I download firmware without using the Cypress EZ-USB control panel if I am not using an EEPROM in a design?

Response:It is not recommended to have such a design.Omitting an EEPROM from a design requires user to run a script file to download firmware to the device when it comes up with our default VID/PID (0x04B4, 0x8613), which is not for use in an end product.If all of our customers used this method, each would be linking their drivers to it, replacing someone else's link.When designing a consumer product it is recommended to use a small EEPROM and put a proprietary VID/PID in it.When the device enumerates with the proprietary VID/PID on the small EEPROM, we can run a script or use the EZ LOADER method to download the firmware into the device and enumerate it with a new VID/PID and bind it to a custom driver.

Please refer the application note EZ LOADER Custom USB Firmware Loader Driver and the KB article Firmware Download Using Script for EZ LOADER and the Script method of downloading firmware respectively.
 
Implementation of ATA/ATAPI-6 standard through GPIF

最近更新：08/12/2010 
Question:Does CY7C68013A support ATA/ATAPI-6 standard (through GPIF)?

Answer:Yes, FX2LP can support ATA/ATAPI-6 standard through GPIF.Infact, we have a reference design, CY4611B - USB 2.0 USB to ATA Reference Design which demonstrates this.More details of the reference design may be found in the following link.

CY4611B - USB 2.0 USB to ATA Reference Design
 
Error codes into string when using CyAPI.lib

最近更新：04/28/2010

Question:How to convert error codes (CCyUSBEndPoint::NtStatus) into meaningful string when using CyAPI.lib?

 

Response:The error codes can be converted into strings by using the CCyUSBDevice::UsbdStatusString(ULONG stat, PCHAR s).The variable ‘stat’ is the UsbdStatus error code obtained from NtStatus and ‘s’ holds the converted meaningful string.

CyUSB.sys Support For WinServer 2003

最近更新：01/04/2010

 
Question: Does cyusb.sys support windows Server 2003 ?

Answer:The cyusb.sys driver was not designed keeping in mind server operating systems and hence, was not tested on Windows Server 2003.CyUSB.sys was only tested on the list of Operating Systems that we have specified in our release notes i.e. Windows XP and Vista, both 32 and 64 bits.The Vista version of the cyusb.sys driver was also tested successfully on Windows 7 OS .
 
I2C Read using FX2/FX2LP

最近更新：01/10/2010
Question:How is I2C read implemented in the FX2/FX2LP?

Response:I2C read implementation is illustrated in the file i2c.c. This file is located in the path \Cypress\USB\Target\Lib\LP\i2c.c

In this file, the implementation of read occurs in the isr.The I2C_Read function only sends the Read Command and changes the I2C.PktStatus to I2C_PRIME.

The I2C enters the ISR every time a byte of data is successfully transferred when the done bit is set high.

So the first time the following section of code is executed

case I2C_PRIME:
I2CPckt.dat[I2CPckt.count] = I2DAT;
I2CPckt.status = I2C_RECEIVING;
if(I2CPckt.length == 1) // may be only one byte read
I2CS |= bmLASTRD;
break;

So, whatever is the data that has been read is stored to I2CPckt.dat and the status is changed to I2C_RECEIVING.So, incase there is more data intended to be read, the following section of the code is executed the next time the ISR is serviced.

case I2C_RECEIVING:
if(I2CPckt.count == I2CPckt.length - 2)
I2CS |= bmLASTRD;
if(I2CPckt.count == I2CPckt.length - 1)
{
I2CS |= bmSTOP;
I2CPckt.status = I2C_IDLE;
}
I2CPckt.dat[I2CPckt.count] = I2DAT;
++I2CPckt.count;
break;

Frequency input for timers in EZ-USB

最近更新：01/10/2010
Question:What is the maximum acceptable frequency that can be input for timers in EZ-USB?

Response:By default, the 8051 counters increments every 12 clock cycles.However, with the EZ-USB, counters can be made to increment every 4 clock cycles by a bit setting in the clock control register.The maximum CPU clock in the EZ-USB is 48MHz.The clock increments on a negative edge on the T0/T1/T2 pin.So, it would need 4 clock cycles to sample a high on the input pin and another 4 clock cycles to sample a low on the same pin, to increment.Hence the maximum frequency that can be input to the timer/counter should be CPU_clock/8 or CPU_clock/24 depending on the bit setting in the clock control register.Hence, the maximum frequency that can be input can be as high as 6MHz
 
CCyUSBDevice::Reset ( ) function of CyAPI

最近更新：04/01/2010

Question :Is calling the CCyUSBDevice::Reset () function equivalent to performing a hardware reset?

Response:No, the CCyUSBDevice::Reset () function is not equivalent to performing a hardware reset.This Reset triggers a USB Bus reset and if one wishes to execute a specific set of events on this Reset, it can be done within the USB reset ISR[ ISR_Ures].For differences between the various Resets, please refer Chapter 7 ‘Resets’ in the EZ-USB TRM.

Debugging GPIF Appliclations

Question:What is the best way to debug my GPIF application?

Response:The recommended way to debug any GPIF application is to use a logic analyzer to examine the peripheral interface. Also, turn on the GSTATE bit in the IFCONFIG register to allow you to use PE[2:0] as a way of monitoring the state of the GPIF engine. This in conjuction with monitoring the GPIFDONE bit in the GPIFIDLECS register will tell you what state the GPIF is locking up in, etc. It's also a good idea to use vendor commands that return the value of GPIFTC[B3:B0], GPIFIDLECS, etc. This is a less intrusive way of monitoring register values than the Keil debugger.
 
Combine code and data space in external SRAM

Last Updated: 08/28/2009

Question: How can I connect an external SRAM, with PSEN# and OE# or-ed together, in order to combine code and data space (for debugging)?

 

Response: In order to combine off chip code and data memory, you can connect the RAM_OE to the FX2LP's OE# (pin 38), RAM_WR to the FX2LP's WR# (pin 41) and the RAM_CS to the FX2LP's CS# (pin 42). Please make sure that the pin EA (pin 35) is held high. This would eliminate the use of PSEN# and an OR logic.

Host Application example projects in C++ and C# for FX products

最近更新：01/03/2010 
Question:Where can I find host application example projects in C++ and C# for FX products?

Response:The host application example projects in C++ using CyAPI.lib can be found in the path C:\Program Files\Cypress\Cypress Suite USB 3.4.1\CyAPI\examples after you download and install CySuiteUSB_3_4_1_B20.zip in the default path from the link SuiteUSB 3.4 - USB Development tools for Visual Studio.Also the host application example projects in C# using CyUSB.dll can be found in the path C:\Program Files\Cypress\Cypress Suite USB 3.4.1\CyUSB.NET\examples.
 
Single INF file that supports both device and script in Windows XP 32 and 64 bit for FX1/FX2LP

最近更新：12/30/2009

 
Question:Can you provide the single INF that supports both device and script in Windows XP 32 and 64 bit?

Response:Find attached the zip file which contains INF file that support both device and script in Windows XP 32 and 64 bit.It also has the drivers to be used along with the inf file [CYUSBxp32.sys (for WinXP 32 bit) and CYUSBxp64.sys (for WinXP 64 bit)].

Changes needed in the inf for 32 bit Device and Script:

The XXXX and YYYY should be replaced by the device VID and PID in the below line

%VID_XXXX&PID_YYYY.DeviceDesc%=CyUsb.NTx86.5.1, USB\VID_XXXX&PID_YYYY

Similarly the XXXX and YYYY should be replaced by the Script VID and PID in the below line

%VID_XXXX&PID_YYYY.DeviceDesc%=CyFwLoadx86, USB\VID_XXXX&PID_YYYY

Changes needed in the inf for 64 bit Device and Script:

The XXXX and YYYY should be replaced by the device VID and PID in the below line

%VID_XXXX&PID_YYYY.DeviceDesc%=CyUsb.NTamd64.5.1, USB\VID_XXXX&PID_YYYY

Similarly the XXXX and YYYY should be replaced by the Script VID and PID in the below line

%VID_XXXX&PID_YYYY.DeviceDesc%=CyFwLoad, USB\VID_XXXX&PID_YYYY

Also the script name in the INF file has to be changed from “MyDevice.spt” to the respective .spt file name. 

For more information on scripting refer the application note Downloading FX2LP Firmware using CyConsole Script Capabilities - AN50963
 
用于 FX2LP 枚举的固件

最近更新：12/16/2009
Question:Does FX2LP do all the enumeration by itself or user has to do programming?
Response:FX2LP is a general purpose High Speed USB peripheral controller.So user has to write code according to the purpose.We provide the frameworks (pre-written code) which can do enumeration by itself with no extra effort on programming from the customer side.The frameworks can be found in the path C:\Cypress\USB\Target\Fw\LP after you download and install SETUP_FX2LP_DVK_1004.exe from the link

CY3684 EZ-USB FX2LP Development Kit in the default path.You can also find the examples under C:\Cypress\USB\Examples\FX2LP which is based on this framework.To start with you can refer EZ-USB_GettingStarted.pdf and Dvk _Users _Guide.pdf in the same link  CY3684 EZ-USB FX2LP Development Kit.

Enabling External Interrupts in FX2LP

最近更新：10/08/2009
Question:How to enable to external interrupts in FX2LP?

Response:There are 5 external interrupts in FX2LP.They are INT0, INT1, INT4, INT5 and INT6.INT0 and INT1 are alternate functions of Port A pins PA0 and PA1.The alternate function on these pins is enabled by setting bits 0 and 1 of PORTACFG register.These Interrupts are by default active low and level sensitive.They can be made edge sensitive by setting bits 0 and 2 of SFR TCON.The interrupts are enabled by setting bits EX0 and EX1 (bits 0 and 2 of SFR IE).

INT4 is autovectored FIFO/GPIF Interrupt but it can be configured as External Interrupt 4 on 100- and 128-pin EZ-USB only.This can be done by clearing the INT4VEC bit in the INTSETUP register.It is an edge sensitive and active high interrupt and has a dedicated pin.

INT5 is an edge sensitive and active low interrupt and has a dedicated pin.

INT6 is an alternate function of port E pin PE5.The alternate function can be enabled by setting bit 5 of PORTECFG register.

INT4, INT5 and INT6 are enabled by setting bits 2,3 and 4 of SFR EIE.
 
Cypress USB 2.0 to ATA/ATAPI solutions support for more than one IDE device

最近更新：12/08/2009 
Question:Can Cypress USB 2.0 to ATA solutions support  more than one IDE device at the same time?

Response AT2  solution  based on CY7C68300A can only support one ATA/ATAPI device at  a time.
However the  AT2LP solution based on  CY7C68300C/CY7C68301C/CY7C68320C/CY7C68321C chipsets support more than one IDE at the same  time.The entire possible combination of devices supported by AT2LP are given  below

               1.ATA/ATAPI master only

               2.ATA/ATAPI Slave  only                                                                                        

               3. ATA/ATAPI master and ATA/ATAPI slave

               4.CompactFlash only              

               5.ATA/ATAPI slave and CompactFlash or other removable IDE master

CY4615  DVK board  based on CY7C68320C  supports  the above  mentioned  configurations

The CY4611 board based on the FX2 (CY7C68013) chip, can also support two ATA/ATAPI devices at the same time - one set to master and one set to slave.
 
EZ-USB FX2 GPIF Reference Materials

最近更新：12/19/2008

QUESTION:Are there any reference materials for the EZ-USB FX2 (CY7C68013) GPIF engine?

ANSWER:Yes, we have several examples, application notes, and the Technical Reference Manual that you may use as a reference. The examples may be found in the following directory after installing the EZ-USB Development Tools on your system: C:\CYPRESS\USB\Application Reference Materials\Support Information\High Speed Devices\CY7C68013 FX2\Examples. The application notes are posted on our website under USB->High-Speed->Application notes section. We have the source code along with these application notes, which should also be a good reference. The application notes are titled:"Introduction to the EZ-USB FX2 GPIF Engine" and "EZ-USB FX2 GPIF Primer". Along with these resources, you may also want to review Chapter 10 of the Technical Reference Manual.

 

FX2/FX2LP最大传输率

最近更新：09/30/2009
Question:FX2/FX2LP传输率局限在20 MBps，如何挺高传输率？

Response: FX2/FX2LP可以提供USB协议所提议的最大吞吐量。吞吐量大小受到一些参数的影响，诸如连接到主机的设备数量、主机控制器在用、计算机处理速度，等等。

SuiteUSB SDK 中的 Screamer/Streamer 例子可以用来演示FX2/FX2LP的吞吐量性能。使用Screamer/Streamer例子时，你应该让设备运行 CYStream 固件，并选择恰当的设置。

连接到主机的所有设备共享可用的带宽。作为测试的目的，你可以只把该测试设备插入到主机。下列测量结果是在使用CYStream演示程序、CyAPI.lib、并调用CyUSB.sys驱动程序的条件下获得的。

OS:                   Windows XP SP3

CPU:                  2.2 GHZ Core2Duo

EHCI Controller:      Intel ICH8

"Streamed" BULK IN:  ~40.722 MBps

"Streamed" ISOC IN:  ~24.023 MBps
 
Maximum Packet Sizes for FX2/FX2LP in Full-speed Mode.

最近更新：10/05/2009 
Question :The FX2/FX2LP Technical Reference manual says the buffers appear smaller when the FX2/FX2LP runs at full speed and that packets are fixed at 64 bytes for non-Iso types.Does this mean that we cannot take advantage of the larger (slave) FIFO sizes - such as 512 bytes for bulk tranfers - when using a PC that does not support high speed ?
Response:When FX2/FX2LP is full-speed mode, the maximum packet sizes of the endpoints will always be 64 for non-ISO types.Even though the endpoints are physically large, in full speed mode they appear to the programmer as only 64 bytes deep.You will not be able to take advantage of the larger FIFO size.

 

Utilization of the unused GPIF control lines .

最近更新：09/16/2009
Question:Does triggering of the GPIF change the state of the unused control lines?

Response:No, triggering of the GPIF does not change the state of the unused control lines.This is an advantage in a situation when we are using only a few of the GPIF control lines.Let us say, of the 6 available control lines, we are using only 2 for GPIF and the rest 4 can be used for other purposes.When the GPIF is idle, we can manipulate the state of the unused 4 control lines using the GPIFIDLECTL register.Even when the GPIF is triggered, the unused control lines will retain the value they were initialized to in the GPIFIDLECTL register.

 

Address Valid Time When Using AUTOPTR1/2 for External Data Memory Access

最近更新：06/26/2009 
Question:How to address external memory when using the AUTPOPTR1 or AUTOPTR2 in FX2/FX2LP  8051?

Response:When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 will only be active while either RD# or WR# are active.The address of AUTOPTR2 will be active throughout the cycle and meet the address valid  time which is based on the stretch value. Scetion 9.3 and 9.4 of the latest  version of the datasheet provides  this information.

Config0 byte in 12C EEPROM showing bit 2 setting

最近更新：06/26/2009

 
Question:Why do the examples for the Config0 byte in 12C EEPROM show setting bit 2?

Response:In the early versions of FX2 this bit was used to permanently set the operation frequency of the 8051.In later versions of the silicon it was altered to allow the 8051 to set up and change the CPU clock speed.As a result, the production silicon does not use this configuration bit.The 8051 starts at 12 MHz and the 8051 has the ability to change the frequency through the CPUCS register.The examples allow both early and later version of the silicon to start the clock speed at the desired rate.These bits are not used in the current production silicon.

 
在 FX2 开发套件板上对串行 EEPROM 编程

最近更新：08/28/2009

 
Question: 我怎样在FX2开发板上对串行EEPROM编程？

Response:

大容量串行EEPROM编程方法：

To program the large serial EEPROM on the CY3681 FX2 Development Kit board, please use the following sequence (Refer to the "FX2 Getting Started.pdf" file, included in the kit software, section 5.4 for switch context).These steps will allow you to recover from a corrupt EEPROM and successfully program a new EEPROM image every time.

1) Unplug the USB cable from the dev board
2) Set Switch2 to Off (Disable EEPROM boot)
3) Set Switch1 to Large (Select the large EEPROM)
4) Connect the USB cable to the development board
5) At this point you should see the development board enumerate as "Cypress EZ-USB FX2 (68613) - EEPROM Missing" under Windows Device Manager
6) Set Switch2 to On (Enable EEPROM boot)
7) Open the EZ-USB Control Panel, ensuring that the Target drop-down select field is "FX2"
8) By clicking on the "Download" button, navigate your way to the Vend_Ax directory and download Vend_Ax.hex
9) On the EZ-USB Control Panel's "Vend Req" Toolbar, use the following to fill in the required fields:

Req=0xA9 (The 0xA9 vendor request is used to access large EEPROMs that have a dual-byte addressing scheme)
Value=0x0000
Index=0xBEEF
Length=16
Dir=1 IN

10) Press the "Vend Req" button to verify that the 16 bytes displayed in the data window are NOT CD CD CD .. CD. If the data is all CD, then it cannot read the EEPROM (Not a large type such as the 24LC64).Otherwise, continue.

11) On the EZ-USB Control Panel's "Vend Req" Toolbar, use the following to fill in the required fields:

Req=0xA9
Value=0x0000
Index=0xBEEF
Length=1
Dir=0 OUT
Hex Bytes= 00

12) Press the "Vend Req" button to blast the first byte in the EEPROM.

13) On the EZ-USB Control Panel's "Vend Req" Toolbar, use the following to fill in the required fields:

Req=0xA9
Value=0x0000
Index=0xBEEF
Length=1
Dir=1 IN

14) Press "Vend Req" to verify that the first byte in the EEPROM is 0x00
15) Unplug the USB cable from the development board
16) Connect the USB cable to the development board
17) At this point you should still see the development board enumerate as "Cypress EZ-USB FX2 (68613) - EEPROM Missing" under Windows Device Manager because the first byte in the EEPROM is 0x00 (an invalid signature byte).
18) To program the EEPROM image, on the EZ-USB Control Panel, press the "EEPROM" button and navigate to and select filename.iic, where filename is the name you have given to your EEPROM image
19) Wait for the EEPROM file open dialog to completely disappear (1-2 minutes)

20) To verify the EEPROM load, repeat steps 9) and 10) above to read the EEPROM and verify that the first eight bytes contain a sequence starting with 0xC2 and followed in reverse endian by either our default VID/PID/DID, or your own if you used the VID and PID parameters in the hex2bix utility when you created your .iic file.

21) If the EEPROM was programmed correctly, then plug out the board, set switch2 to On and switch1 to Large and your board should load and enumerate with your firmware.

The steps for programming the Large EEPROM on the CY4611 FX2 ATA reference design board are the same as above, except that you should ignore the Switch1 instructions and substitute the JP1 jumper for Switch2.

小容量串行EEPROM编程方法：

To program the small serial EEPROM on the CY3681 FX2 Development Kit board, please use the following sequence (Refer to the "FX2 Getting Started.pdf" file, included in the kit software, section 5.4 for switch context).These steps will allow you to recover from a corrupt EEPROM and successfully hand program a small EEPROM every time.

1) Unplug the USB cable from the dev board
2) Set Switch2 to Off (Disable EEPROM boot)
3) Set Switch1 to Small (Select the small EEPROM)
4) Connect the USB cable to the development board
5) At this point you should see the development board enumerate as "Cypress EZ-USB FX2 (68613) - EEPROM Missing" under Windows Device Manager
6) Set Switch2 to On (enable EEPROM boot)
7) Open the EZ-USB Control Panel, ensuring that the Target drop-down select field is "FX2"
8) By clicking on the "Download" button, navigate your way to the Vend_Ax directory and download Vend_Ax.hex
9) On the EZ-USB Control Panel's "Vend Req" Toolbar, use the following to fill in the required fields:

Req=0xA2 (the 0xA2 vendor request is used to access small EEPROMs that have a single-byte addressing scheme)
Value=0x0000
Index=0xBEEF
Length=16
Dir=1 IN

10) Press the "Vend Req" button to verify that the 16 bytes displayed in the data window are NOT CD CD CD .. CD. If the data is all CD, then it cannot read the EEPROM (not a small type such as the 24LC00).Otherwise, continue.

11) On the EZ-USB Control Panel's "Vend Req" Toolbar, use the following to fill in the required fields:

Req=0xA2
Value=0x0000
Index=0xBEEF
Length=1
Dir=0 OUT
Hex Bytes= 00

12) Press the "Vend Req" button to blast the first byte in the EEPROM.

13) On the EZ-USB Control Panel's "Vend Req" Toolbar, use the following to fill in the required fields:

Req=0xA2
Value=0x0000
Index=0xBEEF
Length=1
Dir=1 IN

14) Press "Vend Req" to verify that the first byte in the EEPROM is 0x00
15) Unplug the USB cable from the dev board
16) Connect the USB cable to the dev board
17) At this point you should still see the dev board enumerate as "Cypress EZ-USB FX2 (68613) - EEPROM Missing" under Windows Device Manager because the first byte in the EEPROM is 0x00 (An invalid signature byte).
18) On the EZ-USB Control Panel's "Vend Req" Toolbar, use the following to fill in the required fields:

Req=0xA2
Value=0x0000
Index=0xBEEF
Length=8
Dir=0 OUT

19) Use the Hex Bytes field to enter the sequence C0 followed by VID(LSB), VID(MSB), PID(LSB), PID(MSB), DID(LSB), DID(MSB), and configuration byte that you want.If you use the sequence C0 B4 04 81 00 00 00 00, then the board will automatically enumerate and load the default Keil Monitor.This is useful for debugging.

20) To verify the EEPROM load, repeat steps 9) and 10) above to read the EEPROM and verify that the first eight bytes contain a sequence as mentioned in step 19) above.

21) If the EEPROM was programmed correctly, then plug out the board, set switch2 to On and switch1 to Small, plug in the board, and your board should load and enumerate as a "Cypress EZ-USB FX2 Development Board".The green BKPT/Monitor light should also be lit, indicating a successful download of the default Keil monitor program.

 
Dynamic Switching of the FX2 CPU Clock.

最近更新：06/26/2009

 
Question:Is it possible to change clock frequency while the chip is running?

Response:Yes.Bits 3 (CLKSPD0) and 4 (CLKSPD1) of the CPUCS register are used to set the CPU clock speed.At power-on-reset, these bits default to 00 (12 MHz).Firmware may modify these bits at any time.

CLKSPD1/CLKSPD0 -> CPU Clock
---------------------------------------
00              -> 12 MHz (Default)
01              -> 24 MHz
10              -> 48 MHz
11              -> Reserved

See table 15-4 on page 15-14 of the Technical Reference Manual.

 
GSTATE[2:0] and PE[2:0]

最近更新：08/28/2009
Question: If I turn on the GSTATE[2:0] signals, does this mean that I lose PE[2:0] as GPIO?

Response:Yes, PE[2:0] will no longer be available as GPIO. 

Unused GPIO Connections in the FX2

最近更新：08/28/2009
Question:
The CY7C68013 EZ-USB FX2 has four GPIO ports on the 128-pin part.Can the unused GPIO pins be left open or should they have some type of termination?

Response:
Unused GPIO pins should be tied to ground.Floating inputs can cause unnecessary noise and power consumption.

 
Specifiying the Register Bank for the ISR

最近更新：08/28/2009

 
Question: Will it cause a problem if I have an ISR that calls another function and I don't specify which register bank the INT0# ISR uses with the "using" statement?What is the importance of specifying the register bank for the ISR?

Response:Register banks and ISRs are key to handling context switching rapidly in the 8051 family.Context switching is the activity involved in moving from one task to another when an interrupt occurs.Typically, if you don't use the 'using' directive it shouldn't be a problem.

注意：Calling a function from within an ISR could potentially have some shortcomings.

Can I Set the GPIFTC[B3:B0] Registers to Any Value?

最近更新：08/05/2009
Title:Setting Registers

Question: Can I set the GPIFTC[B3:B0] registers to any value?

Response:
You can set the GPIFTC[B3:B0] registers with any value from 1 to 2^32-1, since they represent a 32-bit field.0 is not a valid entry.

 

AUTODAT1/2 SFR Version Usage in the CY7C68013 EZ-USB FX2

最近更新：06/26/2009

 
Question:Can the Special Function Register (SFR) version of the AUTODAT1/2 be used in FX2?

Response:The SFR versions of the AUTODAT1/2 have been de-featured for quite some time.Instead, please use the MOVX versions, which are XAUTODAT1/2.The performance decrease of using a MOVX instruction instead of a MOV instruction is miniscule, and will not affect overall performance of the device and application.

All mentions of SFR versions have been removed from FX2 documentation to avoid user confusion.

 
BULK TRANSFER Rate with CY7C68013

最近更新：04/01/2009

 
Question: Which registers must be set to guarantee 4x512 bytes per microframe data rate?

Response: Bulk mode bandwidth is not guaranteed. For guaranteed bandwidth, Isochronous mode transfers should be considered. However, to provide optimal throughput, set the buffering for 4x512 or quad buffering. Indeed, for many microframes, the host can schedule more than 4 Bulk packet transfers or it may schedule less than the 4 Bulk transfers. Although Bulk transfers can be bursty in nature, the packet data is guaranteed, since packet retries are performed on packet transfer errors.To set an endpoint to be double, triple, or quad buffered, you will need to set bits 1 and 0 of the EPxCFG register with the values as shown in Table 15.6.2- Endpoint Buffering Amounts of the FX2 Technical Reference Manual.Bit 3 of this register will also set the size of the buffer, for example Endpoints 4 and 8 can only be 512 bytes.Endpoints 2 and 6 are selectable.The values for this register are set with 0 = 512 bytes and 1 = 1024 bytes. The FX2 Technical Reference Manual can be downloaded at the following URL:http://www.cypress.com/?rID=14667

Changes Needed when Switching from 24C02B EEPROM to 24xxxx EEPROM

最近更新：04/01/2009

 
Question:Why does the EEPROM does not accept the data packet when doing a write, especially while changing from  eval board to a own  design ?

Response:The reason is the following:The symptoms are that when the eval board comes up the I2C looks at address A2 or A4, and when the customer design comes up the I2C looks at A0, which is invalid. The 24C02B does not use A0, A1, A2, meaning there is no internal connection, so any address supplied to the EEPROM chip is viable.On the other hand the 24xxxx uses these pins and these pins must be physically tied to address 2 (A0=0, A1=1, A2=0).If this is not done than the chip will not accept the data packet.Verify that you have connected A0-A2 on the EEPROM before trying to write data.

Detecting FX2 and FX2LP

最近更新：04/01/2009

 
Question:Is there anyway of determining which device is running, FX2 or FX2LP?

Response:Reading the REVID register (E60A) would be one way.FX2LP should be "01" whereas FX2 is "05".Another way would be to write a register that is in one chip and not in the other and read it back.For example, one of the ECC registers like ECC_CONFIG (E628) bit 0, which is present in FX2LP but is not there in FX2.

 
EEPROM Recommendation

最近更新：04/01/2009

 
Question:Does Cypress still recommend 64K EEPROM as noted in the CY7C68013 FX2 CY3681 DVK manual?

Response:The type of EEPROM used with the FX2 (CY68013) varies with application.The 24LC64 64k EEPROM is used when the firmware is stored in, and loaded from, the EEPROM at startup.This device is the largest useful size because it matches the loadable RAM area (8K bytes) of the FX2.A smaller EEPROM can be used depending on the size of the firmware object.

If the firmware is loaded from the host, then a 24LC00 (16 bytes) is sufficient for storing VID/PID/DID and configuration byte information.
 
FX2 Logic

最近更新：04/01/2009

 
Question:Does FX2LP need to see a zero-to-one transition on the AUTOIN/AUTOOUT mode bits for correct operation?

Response:FX2 logic needs to see a zero-to-one transition from AUTOOUT= 0 to AUTOOUT = 1 and a zero-to-one transition from AUTOIN=0 to AUTOIN=1 to configure the endpoint in AUTOOUT/AUTOIN mode.When FX2 powers on, the AUTOOUT/AUTOIN bits are cleared.It would seem that the firmware only needs to straight away set the AUTOOUT/AUTOIN bits to configure the endpoint for AUTOOUT/AUTOIN mode.However, because power is still applied, successive downloads of firmware will not cause the FX2 logic to see this zero-to-one transition.So, we recommend manual assertion of the zero-to-one transition in firmware to ensure correct behaviour every time.
 
State of Address Lines During Reset in FX2LP

最近更新：04/01/2009

 
Question:During the RESET are the Address outputs released?If not, in what state are.

 

Response:During the RESET the address lines also are in driven state.So ?Always Driven?as mentioned in the CY7C68013A datasheet.
 
Distinction between FX2 and FX2LP by firmware

最近更新：03/05/2009

 
Question:How can firmware distinguish if it is running on a FX2 or FX2LP?Are there any registers that we could check?

 

Response:Yes, you could read the REVID register (E60A) to distinguish between FX2 and FX2LP.The Chip Revision ID for FX2LP should be "01" whereas FX2 is "05".An alternative would be to write to a register which is present in one chip and not in the other and then read it back.For example, you can write and then read from one of the ECC registers like ECC_CONFIG (E628) bit 0 which is present in FX2LP but not there in FX2.Reading the REVID register instead would be more appropriate.

 
Application of T0/T1/T2 Pins in FX2

最近更新：02/25/2009

 
Question:
What is the typical application for signals T0/T1/T2 (pins 29-31 in the 128-pin package) in FX2?

Response:
Instead of using the internal CLKOUT of the CPU, timer, 0-2 can use the T0-T2 pins as an event counter.An external clock input is supplied to T0-T2 to increment the timer 0-2 count.
 
Address line configuration setting in GPIF Designer

最近更新：02/24/2009

 
Question:

I am using the GPIF Designer.I use PE7 for another hardware function .I have 'right-clicked' in the Block Diagram tab and cleared the ADR8 box (the line went grey).But when I look at the gpif.c file generated I see:

// Configure GPIF Address pins, output initial value,
PORTCCFG = 0xFF; // [7:0] as alt. func.GPIFADR[7:0]
OEC = 0xFF; // and as outputs
PORTECFG |= 0x80; // [8] as alt. func.GPIFADR[8]
OEE |= 0x80; // and as output

This seems to be setting PE7 as an output (I need it as an input).I can obviously manually edit gpif.c, but if someone modifies the design later and regenerates gpif.c this will cause a problem.

Is there a way to stop GPIF Designer from affecting PE7?

Response:

Please note that the Address line configuration setting have no impact on the rest of the program or on the waveform descriptor data generated by the Tools | Export function.They serve only to provide a visual reminder of the actual hardware application for which the waveform descriptors was designed.For more information please refer Help → This Tool → ADR line configuration. 
 
I2C Clock Rate at Startup for FX2LP

最近更新：02/12/2009

 
Question:Can the clock rate of the I2C device be changed to 100KHz after start up?Must it be 400KHz at start up to properly enumerate?

Response:The bus frequency defaults to approximately 100 kHz for compatibility, and it can be configured to run at 400 kHz for devices that support the higher speed.Setting bit 0 of I2CTL (E67A) register to 1 causes the EZ-USB to drive SCL at approximately 400 kHz.Once the CPU is running, firmware can modify this I2CTL.0 bit. 

Any internal pull up/downs on Port I/O pins

最近更新：12/19/2008

 
Question:
Are there are weak internal pull ups or pull down resistor on the FX2/FX2LP Port pins ?

Response:
No.  There are no internal pull ups or pull down resistor on the FX2/FX2LP Port pins .

 
Booting from the EEPROM (AT24LC128) is Unreliable

最近更新：12/19/2008

 
Title:Booting from the EEPROM (AT24LC128) is Unreliable

Question:
I am trying to use an AT24LC128 serial EEPROM and the boot process from the EEPROM is not reliable.

Response:
The FX2 (CY7C68013) part defaults the serial EEPROM's clock to 100 KHz. The 3.3V version runs at 400 KHz. The configuration byte of the EEPROM is the eighth byte in the EEPROM and the LSB of this byte sets the speed of the EEPROM clock.To clock the EEPROM at 400KHz you must set the LSB of this byte.Once that is done the AT24LC128 serial EEPROM will function with the FX2 part.
 

Bus Capacitance Capability (Address, Data and Some Clock Signals) for the CY7C68013-128AC

最近更新：12/19/2008

 
Title:Bus Capacitance Capacity

Question:
I am trying to figure out if I will need buffers for the data bus for the CY7C68013-128AC part.I could not find the maximum output capacitance allowed for the bus for the specified bus timing.I plan to use the part at the 48 MHz clock speed.Could you please provide me with the following information:

1.)Maximum allowable capacitance for the data bus.
2.)Maximum allowable capacitance for the address bus.
3.)Maximum allowable capacitance for the main clock output pin
4.)Maximum allowable capacitance for the IFCLK clock pin.

Response:
The characterization data is performed with a 50 pF load on all of the pins with the spec limit on the current of ± 4 mA.

CY7C68013 - Unable to enumerate

最近更新：12/19/2008

 
Question: I am using the CY7C68013 device on my own board. However, I am unable to get the PC to recognize my board. It will not go through the enumeration process. Any suggestions?

 

Response: Connections that will stop the enumeration process are as follows:

 

1) Power missing. If any of the AVCC and all VCC pins are not powered with 3.0 to 3.6 volts the part may not start.
 
2) EA connected external memory without programs loaded into the external memory. Connecting EA to ground will link to internal memory. If an EEPROM is used with EA high you cannot do a download from EEPROM to external memory and must have external EPROM (or other non-volatile memory) programmed. It is best to start with EA at ground.
 
3) No pull-ups on SCL and SDA. The way the chip works is it will look for an EEPROM on the SCL, SDA lines. To do this they look for inactivity on these pins and if no activity the chip will take control of the pins and look for an EEPROM at address 0 or address 1. If no EEPROM is present then it will start with defaults. Therefore you must have pull ups to show no activity (high is idle state). 
4) Proper crystal. The start up load capacitance is wide, normally you have between 20 and 33 pF with a matched crystal. We use 22 pF with a crystal made for 22 pF, designs have powered up with 33 pF matched to 33 pF load capacitance crystal. The drive level of the crystal must be at least  0.50 mW.
5)  Ground the appropriate reserve pins (follow the data sheet). There are test mode pins if not connected per the data sheet some will be floating or high and the design may be in a test mode and not communicate.
6) If the chip has no EEPROM then it will not depend on address/data lines, all port I/O will be inputs and not matter.
7) If wakeup starts in high, the part is allowed suspend for default conditions, low inhibits it. The capacitor and resistor used in the dev kit allows the FX2 to inhibit wakeup at start up and allows the clock to show on the sc

 

CY7C68013 Serial EEPROM Read

最近更新：12/19/2008

 
Title:CY7C68013 Serial EEPROM Read

Question:
Is there a way to read the serial EEPROM (EEPROM with VID/PID) from the host?Is there a way to read the serial EEPROM using the 8051 and then relay the info to the host using an endpoint?

Response:
Download the Vend_Ax example firmware (c:\cypress\usb\examples\fx2\vend_ax) with the EZ-USB control panel and use the Vend Req toolbar to read the serial EEPROM on the board.

Use the 0xA2 for a small (LC00) EEPROM and 0xA9 for a large (LC64) EEPROM.Specify the offset with the value field (such as 0x0000), the direction of EEPROM access (i.e., IN to read the EEPROM), and how many bytes to read.

There should be a memory dump type display of the data read from the serial EEPROM in the data area of the control panel windows.if a string of "CD CD CD .." appears, then the access to the EEPROM failed.Try again with 0xA9 if 0xA2 was used and vice versa.Also, verify that the EEPROM enable jumper is installed.

For serial EEPROMs programmed for VID/PID only enumeration, the VID/PID will be in the first bytes of the EEPROM.If the serial EEPROM contains a complete program, then dump the bytes at offset of the device descriptor of the program.The program's link map listing (.m51) file is used to determine the correct offset.
 
ope.

Can I Connect 5 Volt Logic to the FX2?

最近更新：12/19/2008

 
Title:5V Logic and the FX2

Question:
Can I connect 5 Volt logic to the FX2?

Response:
Yes. The FX2 is 5 Volt tolerant on its logic inputs and drives outputs at a minimum of 2.4 Volts.You may connect inputs to pull ups of 5 volts, but you must guarantee that the input does not exceed 5.25 volts.Outputs must not exceed Vcc+0.5 volts.For a 3.3 volts, Vcc the output pull ups must not exceed 3.8 Volts.

Can I Control the Impedance of the CY7C68013 Using a Double-sided PCB?

最近更新：12/19/2008

 
Title:Controlling the Impedance of the CY7C68013 Using a Double-sided PCB

Question:Can I control the impedance of the CY7C68013 using a double-sided PCB?

Response:The CY7C68013 needs to use four layer boards to control the impedance.We have not seen any boards control the impedance well enough without at least four layers.We lay out our kit boards this way and run the D+/D- lines near the ground layer.

Can the 8051 Directly Control the GPIF CTLx Lines When the EZ-USB FX2 is in GPIF Mode?

最近更新：12/19/2008

 
Title:Using the 8051 to Control GPIF Lines

Question: Can the 8051 directly control the GPIF CTLx lines when the EZ-USB FX2 is in GPIF mode?

Response: Yes, the 8051 can control the GPIF CTLx lines directly through firmware, but only when the GPIF engine is in the IDLE state.The 8051 accesses the CTLx lines through the GPIFIDLECTL register.

Changing the GPIF Waveform Descriptors for the CY7C68013 EZ-USB FX2 On the Fly

最近更新：12/19/2008

 
Title:Changing the GPIF Waveform Descriptors

Question: What should I be aware of when changing the GPIF waveform descriptors in the middle of a transfer?

Response: GPIF waveform locations should not be changed while the GPIF is in the middle of a transfer.The firmware should first check that the GPIF is IDLE (using if (GPIFTRIG & 0x80)).A premature abort (GPIFABORT=0xFF) may also help to ensure that the GPIF is at a ground-zero state.
 
Clear endpoint FIFO''s for the EZ-USB FX2

最近更新：12/19/2008

 
TITLE:Clearing  Endpoint FIFOs

 

QUESTION: How do I clear the endpoint FIFO's so that I can start with an empty/clear FIFO for the EZ-USB FX2?

 

ANSWER: The easiest way to clear the buffers is with a FIFORESET.You might want your application software to send a vendor command that you implement in firmware to reset and then re-arm the buffers. In order to reset an endpoint FIFO, write 0x80 to this register to NAK all transfers from the host, then write the  endpoint  number to this register (0x02, 0x04, 0x06, or 0x08) to reset an individual FIFO (i.e., to restore endpoint FIFO flags and byte counts to their default states).  Then write 0x00 to clear the NAKALL  bit  and restore normal operation.Refer to section 5.5.4 (FIFO reset) of the Technical Reference Manual for  further information on this register  usage.

 

You also need to ensure after performing a FIFORESET that you are re-arming the OUT endpoints. For OUT endpoints, you need to arm the buffers to let the SIE take control of them, and accept data from the host.

Decrementing the Transaction Counter in the FX2

最近更新：12/19/2008

 
Title:Decrementing the Transaction Counter

Question:
Is it possible to decrement the transaction counter without passing through the IDLE state?

Response:
The GPIF state machine does not need to transition through the idle state in order to decrement the transaction counter.Any "activate" or "next data" in the state causes a decrement of the transaction counter.It is only in the IDLE state that the GPIF state machine looks at the DONE bit in the GPIFIDLECS register to see if the transaction count has expired or if the waveform explicitly tests for TC in a decision point.

 
Default state of CTL outputs

最近更新：12/19/2008

 
Title:Default state of CTL outputs

Question:
When the FX2LP is configured to operate in GPIF mode (IFCONFIG[1:0] set  to 10b) what is the default state of the CTL outputs?

Response:
The default is as set in the GPIFIDLECTL register as the GPIF is in an idle state. The default settings of this register is 0xFF (high).   Hence when the FX2LP is configured to operate in GPIF mode (IFCONFIG[1:0] set  to 10b) the default state of the CTL outputs is 1.

Device Enumerates as High-speed but Renumerates as Full-speed

最近更新：12/19/2008

 
Title:Device Enumerates as High-speed but Renumerates as Full-speed

Question: My device enumerates as a high-speed device but when it renumerates it comes up as a full-speed device.

Response: The polarity of your WAKEUP# pin must match that of the WUPOL bit of the WAKEUPCS register.

The WUPOL bit default value is 0.

If the WAKEUP# pin in your design is pulled low and the and the WUPOL is default, the pin is active low.Therefore, you are holding the pin active.You can either change your board to pull the WAKEUP# pin high or change the firmware to make the pin active high.

If the WAKEUP# pin on your design is pulled high, you should not need to change the WUPOL bit from its default.

To change the firmware, add the line "WAKEUPCS |= bmWUPOL;" statement in the TD_Init() routine in your periph.c file.This will allow suspend and it will allow high-speed renumeration.

 
Code and Enumeration Errors When Writing Code to an EEPROM

最近更新：12/19/2008

 
Title:Code and Enumeration Errors

Question:
I'm using an EZ-USB FX2 with an AT24C64 EEPROM attached.When I download my code through the soft download feature, the device enumerates correctly and behaves perfectly.When I write the code to the EEPROM, however, I have problems.

The first time I cycle power, the device enumerates correctly and performs as it is supposed to.The second and all succeeding applications of power cause it to enumerate in Win2K as "USB Device!"The code will also not run correctly.

The first eight bytes in the EEPROM are:
"B2 47 05 31 21 00 00 00"

What could be wrong?

Response:
The first byte must have been corrupted.The first byte needs to be C2 for firmware boot load, and C0 for VID/PID/DID load.

 
Do the EZ-USB FX2 and the CY3681 Developer Kit Support USB 1.1?

最近更新：12/19/2008

 
Title:USB 1.1 Support

Question:
I would like to order EZ-USB FX2 and the CY3681 developers kit.But I'm not sure whether it can support USB 1.1?Is it backward compatible?

Response:
Yes, you can use the FX2 Developers Kit with a USB 1.1 capable host.The FX2 will operate in fulll-speed mode.

 
EZ-USB FX2 Suspend Interrupt example

最近更新：12/19/2008

 
Question: Is there an example design that shows how to implement the FX2 SUSPEND interrupt when AUTOVECTORing is enabled?

 

Answer: Any of our examples will use the ezusb.lib, which implements the suspend interrupt. Vectoring to this interrupt is handled by the autovector.See C:\Cypress\USB\Target\Lib for source code.

 

If you look in the fw.c file, the software flag "Sleep" is set to TRUE in the suspend ISR in the library.

 
EZ-USB FX2 Performance and Memory Size

最近更新：12/19/2008

 
Title:EZ-USB FX2 Performance and Memory Size

Question:
We want to use the EZ-USB FX2 (CY7C68013-56PVC) chip on our demo board.We intend to use the chip's slave FIFO I/F in synchronous mode.The interface is coupled to an FPGA for further processing.This FPGA will then be the master for the slave FIFOs.

1) How can the local transfer rate of 96 MB/s be achieved?Is it necessary to use the chip in the GPIF mode?With 48 MHz and a 16 bit data bus this would require that Ican transfer a data word (16 bit) per IFCLK cycle.But that is not possible according to Chapter 9 of the Technical Reference Manual.When I look at your example waveforms it seems at least two cycles, or actually three with "State 4", are required.How does this fit into the performance of 96 MB/s?Is it possible to transfer 16-bit data words in one cycle?Or do I need to use one cycle for reading the data, and one cycle to check the FIFO flag and update the FIFO pointer?In this case I only have a performance of 48 MB/s.

2) The setup times for read and write are almost one clock cycle when working with the 48 MHz internal IFCLK.Do I need an additional cycle to set up SLWR or SLRD?Would this further decrease the performance.?I can't see how an inverted clock would help - it makes things even worse.Unless of course I may keep the SLWR or SLRD active during e.g. a packet read where I transfer a data word on each clock cycle!?If I use an external IFCLK, according to the data sheet I get better set-up times, but then I have stronger requirements for the hold time.

3) What is the exact amount of memory inside the chip for the Endpoints EP2, EP4, EP6, and EP8?Are endpoint buffers and endpoint FIFO two separate memory areas or one?Is there a physical memory space for both the FX2 memory space (containing endpoint buffers) and additional 4KB for the FIFOs?

The way I see it, two possbilities exist:a) FX2 memory has space for 3KB (e.g 6x buffers of 512 bytes each); or b) The FIFOs have a space of 4KB.According to your data sheet, an area of 2x 512 bytes in the FX2 memory space is reserved, which explains that a buffer for EP4 and EP8 only can be 512 bytes.The FIFO space (if it is extra space?)has a total of 4KB with no reserved areas, right?

4) When exactly are full and empty flags asserted?On a byte, 16-bit word, USB packet, or user defined packet size level?I need this exact information for both reads or writes to a slave FIFO endpoint.The technical reference manual fails to offer
precise information on that.

Response:
1) The burst rate of 96MB/s can be achieved by running the slave FIFOs at 48 MHz (internal or external clock), while asserting SLWR or SLRD/SLOE for the entire data burst phase.Assuming active low polarity signals, when writing to the slave FIFOs, SLWR should be held low as each word is clocked on the rising edge of IFCLK.The case is similar for reading from the slave FIFOs; SLOE/SLRD should be held low as each new word is read on every rising edge of IFCLK.The technical reference manual assumes a conservative approach as the examples show a word being clocked on every other IFCLK edge.This is for systems that may not be able to abide by the setup and hold times required for a burst phase like what's described above.Clocking a word on every other edge would then reduce the effective burst rate to 48 MB/s.FX2 has the ability to have the FIFO flags assert one word prior to the FIFO becoming full, and one word prior to the FIFO becoming empty.This give the external master additional time to check the FIFO status flags.

2) To achieve the 96MBs, the control signals will have to be active while each word is clocked on the rising edge of IFCLK.

3) The endpoints and FIFOs share one and the same physical memory space.Often you'll see them referred to as "endpoint FIFOs" because they exhibit a dual personality.There are basically two domains the endpoint FIFOs reside in, the USB domain, and the peripheral interface domain.FX2 is able to switch clock domains to pass the packet pointers from one domain to the other, thus seemingly able to "connect" the USB domain to the peripheral interface domain.This is how it maximizes the USB 2.0 bandwidth without need of processor intervention.Sometimes it's a lot easier to think of the FIFO space in terms of buffers, consistent with the different buffering schemes the FX2 can take on.The possible buffering schemes are shown on page 14 of the datasheet.Only EP2 and EP6 can be configured for the larger 1024 FIFO size.

4) The FIFO full and empty flags are byte/word based (depending on how the FIFOs are configured) and therefore represent
byte/word boundaries.For example, if the EP6 full flag is not assserted then there is room for at least one more byte/word in the FIFO.Conversely, if the EP2 empty flag is not asserted, then there is at least one more byte/word to be read by the external master.However, a user level threshold can also be defined for the programmable flag (FLAGA)
 
FX2 WAKEUP# pin

最近更新：12/19/2008

 
主题:FX2 WAKEUP# pin

Question:
Is this edge or level triggered.If it is asserted, how long does it need to remain in this state for triggering a wakeup signal.

Response:
It is level triggered.Minimum pulse width can be brief since it just asynchronously resets a flop. We recommend 20 nS (in reality it's actually a lot less, but this is safe and still relatively small). 
 
Fastest Interrupt Polling Interval in an FX2 Peripheral

最近更新：12/19/2008

 
Title:Fastest Interrupt Polling Interval in an FX2 Peripheral

Questions:
What is the fastest interrupt polling interval that can be requested by an FX2 peripheral?Can the FX2 request service every 125uS?Or is the most frequent polling interval still every full frame (1mS)?

Response:
A USB peripheral does not request service, it merely responds to the host.However, if you are trying to use the SOF to time interrupts in high speed, the SOF occurs every micro frame and can trigger an interrupt.
 
Handling Odd Count Packet Sizes Between an FX2-SX2 16-bit WORDWIDE Interface

最近更新：12/19/2008

 
Title:Handling Odd Count Packet Sizes

Question:
When an odd number of bytes (eg.45 bytes) are sent from FX2's EP2OUT to SX2's EP6IN, the SX2 receives it in word form and it is considered 23 words, since we are using a 16-bit WORDWIDE interface across the two chips.

When the words are converted back to bytes later, the SX2 will multiply it by 2 and becomes 46 bytes in the endpoint FIFO instead of the original 45 bytes originally sent.What should be done to ensure that the byte count in SX2 is 45 bytes in this case?

Response:
Because the FX2 will write in 23 words across the 16-bit interface, one byte will be a 'don't care' byte.One solution is to have the application on the PC side ignore the don't care byte.

A more elegant solution is to create a protocol layer built over the firmware/hardware to communicate how many valid data values are actually contained in the packet, much like how mass storage class devices handle odd packet sizes in a CBW control wrapper.

If the external master has apriori knowledge of byte count information, it can also switch to an 8-bit interface before writing the last byte in the odd size packet, then switch back to a 16-bit interface for successive operations.
 
How Do I Configure the FX2 to Go Into GPIF Mode?

最近更新：12/19/2008

 
Title:FX2 and GPIF Mode

Question:
How do I configure the FX2 to go into GPIF Mode?

Response:
To configure the pins for GPIF mode, the IFCFG[1:0] bits in the IFCONFIG register must be set to 10.
 
How can I do renumeration in firmware?

最近更新：12/19/2008

 
Q :How can I do renumeration in firmware?Ans :At any point of time, by setting DISCON bit in CPUCS register a USB Bus disconnect can be simulated.Clearing this puts the device back on bus re-enumerating the device again, without physically unplugging and re plugging.RENUM bit in CPUCS can be used in Firmware to tell FX2LP to report default descriptors/ customer defined descriptors also.

How can I protect the contents of the EEPROM?

最近更新：12/19/2008

 
Question:
We have a product that uses an external EEPROM for code storage. Is there a way to secure the firmware in the EEPROM so that a hacker cannot read the EEPROM?

Response:
It is not possible to protect the contents of the EEPROM from being read. The download mechanism requires that the EEPROM be readable. There is no encoding scheme available for the download process.

If you designed the device to download via the USB (a C0 load), it would still be possible to monitor the USB traffic to extract the firmware. It is also possible to read the internal memory via a 0xA0 vendor command.

 
Is there a way to send data over the GPIF interface that is NOT from the USB interface/endpoints?

最近更新：12/19/2008

 
Q:Is there a way to send data over the GPIF interface that is NOT from the USB interface/endpoints?

Ans :You can write your data to EP(2,4,6,8) Fifos by the firmware.Then you can trigger GPIF for that EP fifo and transfer data over GPIF
 
Maximum Input frequency for T0, T1, T2 inputs

最近更新：12/19/2008

 
Question:
What is the maximum frequency for the T0, T1, T2 inputs?

Response:
The maximum  input frequency is 1/8th the frequency of the 8051.  e.g., if 8051 is running at 48 MHz then the max input frequency is 6 MHz.  The minimum pulse width high or low is equal to four 8051 clocks. e.g., if 8051 is running at 48 MHz then the minimum pulsewidth is 4 * 20.8 nS.

 
Minimum Pulse Width for external Interrupt pins INT0#

最近更新：12/19/2008

 
Question:
Is there a minimum pulse width for INT0 when it is in "edge" mode?

Response:
The FX2LP having the standard 8051 behavior as far as the external interrupts are concerned have the same pulse width spec'ed  for the external interrupt pins:4 clocks high, 4 clocks low.

The  external interrupt when configured to be edge triggerred it will be triggered either on rising or falling  edge as configured.  Once triggered it will remain in the triggerred state (if set to falling edge it will remain low;  if set  to rising edge, it will remain high) until the INT flag is cleared by the 8051.

 
Multiple GPIF Waveforms for the CY7C68013 EZ-USB FX2

最近更新：12/19/2008

 
Title:Multiple GPIF Waveforms for the CY7C68013 EZ-USB FX2

Question:
Can I use more than four GPIF waveforms with the CY7C68013?

Response:
Yes. However, only four are available at a time and the firmware would be responsible for loading up a new set, prior to activating the GPIF, each time a new set is required.Loading a waveform may consist of simply altering one or more bytes within one or more waveforms or may consist of completely replacing one or more entire waveforms.

SRAM to FX2LP for Memory Expansion

最近更新：12/19/2008 

Question:
How can I wire an SRAM  to the FX2LP  device  for memory expansion. Please provide a pin to pin connect diagram.

Response:
Following is how the SRAM needs to be wired to the FX2LP device.Please use the pin assignments as shown below:

SRAM to FX2
==========
CE# to CS#
OE# to OE#
WE# to WR#
D[7:0] to D[7:0]
A[15:0] to A[15:0]
GND to GND
VCC to VCC

The above is a very standard method of memory exapansion on any 8051 microcontroller

 
Sending Byte Packets Out of GPIF at High Speed

最近更新：12/19/2008

 
Title:Sending Byte Packets Out of GPIF at High Speed

Question:
I'm developing FX2 firmware that uses an EP2 1024 byte Interrupt mode endpoint.I'm trying to send 1024 byte packets out the GPIF at the highest possible speed after determining that the target FIFOs are not full.The GPIF waveform has write enables and mode bits in the CTL signals, so I can't go through IDLE except at packet boundaries without disrupting the target.I've tried AUTOOUT=1, and it seems the FX2 is sending multiple 1024 byte packets without going through IDLE.I need to go through IDLE every 1024 bytes to test the target FIFO.How?

Response:
In this case, you should:

1) Have the 8051 examine the GPIFREADYSTAT register to determine if the target FIFOs are not full.
2) Once this condition has been established, set up the GPIFTC[B1:B0] registers for 1024.
3) Check that the GPIF is idle, then launch the FIFO Read waveform, each time passing through IDLE.
4) Repeat the process for multiple 1024 block transfers.

 
Multi-Buffering of FX2LP endpoints

最近更新：12/19/2008

 
Title:Multi-Buffering of FX2LP endpoints

Question:
Does multi-buffering of an endpoint FIFO increase the depth of the FIFO?Can you please provide further information on multiple buffering and the advantage of having an endpoint multi-buffered?

Response:
As far as the 8051 code is concerned there is NO difference in addressing an endpoint that is multi-buffered.Buffering only allows the 8051/external peripheral to access a buffer space while the other is in transition over USB.Endpoint buffering has no effect on increasing the depth of the FIFO.The depth of the FIFO still is 512/1024 bytes (as configured in EPxCFG register) and your firmware must not address an index greater than 511/1023 while filling the buffer.Internal logic will basically handle the ping-ponging of the buffers.

As explained in section 8.5 (CPU Access to FX2 Endpoint Data) "The CPU can only access the "active" buffer of a multiple-buffered endpoint.In other words, firmware must treat a quad-buffered 512-byte endpoint as being only 512 bytes wide, even though the quad-buffered endpoint actually occupies 2048 bytes of RAM."

For an IN transfer once the data is committed to the USB, the internal logic will assign the next 512 byte buffer as the "active buffer".This is all done by internal logic and is not visible to the 8051.The 8051 must treat the buffer as 512 bytes only.The external master must avoid writing to a full FIFO, or reading from an empty FIFO.The external master can use the FIFO full/empty flag to monitor the state of the FIFO and decide when to stop writing/reading from the FIFO.

 
Serial EEPROM last byte format

最近更新：12/19/2008

 
Question: When I use the "C2 Load" format in my EEPROM, why is the last data record always set to 0x80 and 0x01?

Answer: The last data record must have the MSB of its Length H byte set to 1(0x80), and the Length L byte indicates the Number of Bytes (0x01).The last operation in the C2 Load writes 0x00 to the CPUCS register, which releases the CPU from reset.
Please see section 3.4.3 of the Technical Reference Manual for additional information.

Keywords used:eeprom, C2 load, last, byte,

ID:BHA04061605
 
Turning On the GSTATE[2:0] Signals for Debugging the GPIF State Machine in EZ-USB FX2

最近更新：12/19/2008

 
Title:Turning On the GSTATE[2:0] Signals for Debugging the GPIF State Machine

Question:
For the EZ-USB FX2, how do I turn on the GSTATE[2:0] signals for debugging the GPIF state machine?Where do they come out from the part?

Response:
You can turn on the GSTATE[2:0] signals by setting IFCONFIG.2. The GSTATE[2:0] signals come out on PE[2:0].

Using the CY7C68013 FX2 device, do the T0 through T2 input pins require pull up and pull down resistors, or can they be left floating?

最近更新：12/19/2008

 
Question:

Using the CY7C68013 FX2 device, do the T0 through T2 input pins require pull up and pull down resistors, or can they be left floating?

Response:

Unused pins should not be left unconnected (or floating).Instead, they should be connect to Vcc or Gnd through a ~10K resistor.If there's no chance that an unused pin will ever be configured as an output, then it is safe to tie the pin directly to the appropriate voltage (Vcc or Gnd) without the resistor.

Please note:any unused inputs should be terminated to the appropriate voltage (ground or power).

Using the FX2, can I pull up SDA and SCL line to 5V power supply?

最近更新：12/19/2008

 
Q :I would like to use CY7C68013 with I2C slave device powered by 5v.Can I pull up SDA and SCL line to 5V power supply?

 

A.) Yes, you can use a 5v pull-up for the SCL and SDA pins as they are 5v tolerant.Note that the FX2 can only act as a master and not a slave device.

 
Using GPIF pins for GPIO functionality

最近更新：12/19/2008

 
Question:
Can the GPIF RDYx and CTLx pins be used as generic input and output ports controlled directly by the 8051 when using the part in GPIF  mode??Specifically, can I use the GPIFREADYSTAT registers to sample the states of the RDYx pins, and the GPIFIDLECTL register to control the states of the CTLx output pins?

Response:
Once the part is set to operate in GPIF mode (IFCONFIG[1:0] set  to 10b) the 8051 can determine the current status of the RDYx inputs by reading GPIFREADYSTAT register. The GPIFIDLECTL register sets the CTLx output to be in specific state.So, the 8051 can use this register to output values on
the CTLx output lines when the GPIF is in IDLE state  and use teh GPIFREADYSTAT regsiter read the inputs on RDYx input pins.

So, yes the GPIF CTLx/RDYx can be used as general purpose input and output pins using the GPIFREADYSTAT and GPIFIDLECTL respectively.  Be informed  that CTLx signals will obviously be affected once a waveform (GPIF transfer) is triggered. Otherwise, if the GPIF is IDLE, the mentioned GPIF registers can be used to read/output values on RDYx/CTLx pins.

 
Unused CTLx/RDYx pins when operating in GPIF mode

最近更新：12/19/2008

 
Question:
When FX2/FX2LP is configured to operate in GPIF  mode (IFCONFIG[1:0] set to 10b) can the unused CTLx and RDYx pins be uses as regular GPIO pins as inputs or outputs?

Response:
No.  Once  the part is set to operate in GPIF mode (IFCONFIG[1:0] set  to 10b) some PORT pins are dedicated to GPIF functionality and are used as CTL outputs and RDY inputs. They cannot be used as regular GPIOs. 

Refer to Article 20698 for further information on using GPIF pins as GPIO when in GPIF IDLE mode

 
What is the Purpose of the Macro SYNCDELAY?

最近更新：12/19/2008

 
Title:What is the Purpose of the Macro SYNCDELAY?

Question:
What is the purpose of the macro SYNCDELAY?

Response:
Under certain conditions, some read and write accesses to FX2 registers must be separated by a synchronization delay.The delay is necessary only under the certain conditions that are presented in section 15.14 of the latest version of the TRM (ver.2.0). 
 
What is the maximum I/O port pin sink/source current of FX2LP?

最近更新：12/19/2008

 
Q:What is the maximum I/O port pin sink/source current of FX2LP?

A:The maximum I/O port pin sink/source current of FX2LP is 4 mA.

 
What is the timing rating that is needed for external RAM and ROM (EA=1) for the CY7C68013 (FX2).Is it 20ns?

最近更新：12/19/2008

 
Question:What is the timing rating that is needed for external RAM and ROM (EA=1) for the CY7C68013 (FX2).Is it 20ns?

 

Response:At 48 MHz, an external memory chip used for firmware must have an access time of approximately 44 ns or shorter.The timing diagrams can be found in the FX2 Datasheet.Please refer to the timing diagrams in the AC electrical characteristics of the document.

 
What is this error :"Error 22 :NO CODE MEMORY AT ADDRESS 0045H" from Keil Tool while debugging?

最近更新：12/19/2008

 
This error is reported because 0045H is autovector location populated by EZ-USB hardware.So firmware cannot populate any code there.This error can be neglected.For more explanation and to know how to avoid Keil reporting this error refer this link from Keil:http://www.keil.com/support/docs/863.htm To know more about USB Auto vectored Interrupts refer Page 4-15 of EZ-USB TRM.

Where Can I Find an Example for I2C Operations (FX2)?

最近更新：12/19/2008

 
Title:I2C Operations Example

Question:
Where I can get any example for I2C operations?

Response:
Use the vend_ax example as a starting point  -> C:\Cypress\USB\Examples\FX2\Vend_ax.

Will the Endpoint Going Full Disable the FX2 GPIF?

最近更新：12/19/2008

 
Title:GPIF Disabling

Question:
Will the endpoint at full-speed disable the FX2 GPIF?

Response:
In general, no.

Yes, if the transaction count has expired, or if you've programmed the GPIF to stop when the endpoint goes full by setting EPxGPIFPFSTOP.0 and selecting the full flag of the endpoint as the GPIF fifo flag in the EPxGPIFFLGSEL register.
 
Working Around the Byte Ordering

最近更新：12/19/2008 
Title:Working Around the Byte Ordering

Question:
Is there a way I can work around the byte ordering described in section 10.2.8 of EZ-USB-FX2 TRM?I need it ordered in the same way it would be in FX.

Response:
In FX2 the first byte in the endpoint always goes out FD[7:0] and the second byte always goes out FD[15:8].You must take care to wire the data lines appropriately to your device to achieve the necessary ordering:

FD[7:0] -> second byte port on device
FD[15:8] -> first byte port on device
 
Where Can I Find Help in Creating an EEPROM Image?

最近更新：12/19/2008

 
Title:EEPROM Image Creation

Question:When can I get help on creating an EEPROM image?

Response:
Help can be found in section VII of the "EZ-USB Contents and Tutorial" pdf located in Cypress\USB\Doc\EZ-USB General.

If you only wish to burn a VID/PID into the EEPROM you can use our Vend_ax example and the EZ-USB Control Panel.

If you wish to have your code in the EEPROM remember that it must be linked to internal memory using the BL51 tab of the Keil tools.We recommened not placing code below 0x80 to ensure you do not step on the descriptors and jumptables.

The general process is to create a hex file and then use the hex2bix utility located in the Cypress\USB\bin directory.

For example:
Create a hex file, for example MyFile.hex that is linked to internal memory
Place a copy of the MyFile.hex into Cypress\USB\bin
Open a command prompt and navigate to cypress\usb\bin
Type hex2bix, a syntax help screen will be displayed
Type hex2bix -i -c 0x00 -f 0xC2 -c 0x00 myfile.iic myfile.hex and press enter (the 0xC2 is for the FX2)
Your iic file will be located in the cypress\usb\bin directory.

You can then press the EEPROM button on the EZ-USB Control Panel and navigate to the directory where the image is and download it.

 
eeprom.c and eeprom.h files missing in Vend_Ax example

最近更新：12/19/2008

 
Q:I recently downloaded and installed the CY3684 development kit software.When I try to build the Vend_Ax example I get an error message saying that the eeprom.c and eeprom.h files are missing.What should I do?

Ans:Please note that this is an identified bug in the CY3684/CY3674 development kit software for which a bug report is being submitted.A new release of this software with the fix will be uploaded on the website as soon as possible.Meanwhile, in order to fix this problem, you can include the attached eeprom.c and eeprom.h files with the Vend_Ax example.Please be advised that these files are applicable for both, CY3674 and CY3684 development kits.

 
xdata Memory Range for CY7C68013

最近更新：12/19/2008

 
Title:xdata memory range for CY7C68013

Question:
I am learning how to configure the Keil DK-51 options for EZ-USB FX2 so that I can use all the 64kbytes of Xcode memory, and all the on-chip RAM (0x0000 to 0x1FFF, 0xE000 to 0xFFFF).I assume the on-chip RAM is treated as off-chip Xdata RAM in the uVision2.I can set up the RAM ranging from 0x0000 to 0x1FFF, but I cannot set up RAM from 0xE000 to 0xFFFF.The error message says "Xdata memory range out of bounds".

Response:
Figure 5-3 of the FX2 Technical Reference Manual shows what type of memory is available for off-chip use.The area 0xE000-0xFFFF is unavailable for WR/RD (xdata) accesses.It is available for PSEN code accesses, so if you use an external ROM in this address space you can try linking your code to use the space 0xE000-0xFFFF, operate the code from the ROM, and keep your xdata space below this area for RAM access.