1. Since scan and other test structures are added during and after synthesis, they are not
checked by the rtl simulations and therefore need to be verified by gate level simulation.
2. Static timing analysis tools do not check asynchronous interfaces, so gate level simulation
is required to look at the timing of these interfaces.
3. Careless wildcards in the static timing constraints set false path or mutlicycle path
constraints where they don’t belong.
4. Design changes, typos, or misunderstanding of the design can lead to incorrect false paths
or multicycle paths in the static timing constraints.
5. Using create_clock instead of create_generated_clock leads to incorrect static timing
between clock domains.
6. Gate level simulation can be used to collect switching factor data for power estimation.
7. X’s in RTL simulation can be optimistic or pessimistic. The best way to verify that the
design does not have any unintended dependence on initial conditions is to run gate level
simulation.
8. It’s a nice “warm fuzzy” that the design has been implemented correctly.DICDER -- 博客专栏9Gwl"ppO"U*M'Wl%j^"m R0DICDER -- 博客专栏/A0HDK)a%hZT~DICDER -- 博客专栏~'y?(Z1mG4^DICDER -- 博客专栏r9npZ[DICDER -- 博客专栏+kL6v_8lsDICDER -- 博客专栏!G C;Z
o@!F6ADICDER -- 博客专栏4hZ&C-VS8{Il(U)V``f|K%c0)E
C(q1hxS?i0DICDER -- 博客专栏#EkI H3xbXVv7W7RG;AI2{9n9N
?0DICDER -- 博客专栏5I
caI{DICDER -- 博客专栏$l.|.NQ0q!j6jzHa
checked by the rtl simulations and therefore need to be verified by gate level simulation.
2. Static timing analysis tools do not check asynchronous interfaces, so gate level simulation
is required to look at the timing of these interfaces.
3. Careless wildcards in the static timing constraints set false path or mutlicycle path
constraints where they don’t belong.
4. Design changes, typos, or misunderstanding of the design can lead to incorrect false paths
or multicycle paths in the static timing constraints.
5. Using create_clock instead of create_generated_clock leads to incorrect static timing
between clock domains.
6. Gate level simulation can be used to collect switching factor data for power estimation.
7. X’s in RTL simulation can be optimistic or pessimistic. The best way to verify that the
design does not have any unintended dependence on initial conditions is to run gate level
simulation.
8. It’s a nice “warm fuzzy” that the design has been implemented correctly.DICDER -- 博客专栏9Gwl"ppO"U*M'Wl%j^"m R0DICDER -- 博客专栏/A0HDK)a%hZT~DICDER -- 博客专栏~'y?(Z1mG4^DICDER -- 博客专栏r9npZ[DICDER -- 博客专栏+kL6v_8lsDICDER -- 博客专栏!G C;Z
o@!F6ADICDER -- 博客专栏4hZ&C-VS8{Il(U)V``f|K%c0)E
C(q1hxS?i0DICDER -- 博客专栏#EkI H3xbXVv7W7RG;AI2{9n9N
?0DICDER -- 博客专栏5I
caI{DICDER -- 博客专栏$l.|.NQ0q!j6jzHa
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第三代功率半导体器件测试解决方案 直播时间： 03月06日 10:00
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