原创 VHDL数据类型“小说”

STD_LOGIC --“标准逻辑” 信号形式定义：

‘X’ Forcing Unknown (synthesizable unknown)     ；浮接不定
‘0’ Forcing Low (synthesizable logic ‘1’)          ；低电位
‘1’ Forcing High (synthesizable logic ‘0’)         ；高电位
‘Z’ High impedance (synthesizable tri-state buffer) ；高阻抗
‘W’ Weak unknown                                                   ；弱浮接
‘L’ Weak low                                                              ；弱低电位
‘H’ Weak high                                                             ；弱高电位
‘–’ Don’t care                                                         ；不必理会

STD_ULOGIC (STD_ULOGIC_VECTOR): 9-level logic system introduced in
the IEEE 1164 standard (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘–’)

下面是定义：

 TYPE std_ulogic IS ( 'U',  -- Uninitialized
                         'X',  -- Forcing  Unknown
                         '0',  -- Forcing  0
                         '1',  -- Forcing  1
                         'Z',  -- High Impedance  
                         'W',  -- Weak     Unknown
                         'L',  -- Weak     0      
                         'H',  -- Weak     1     

  -- This is Package STANDARD as defined in the VHDL 1992 Language Reference Manual.
--
--   NOTE: VCOM and VSIM will not work properly if these declarations
--         are modified.

-- Version information: @(#)standard.vhd 

package standard is
 type boolean is (false,true);
 type bit is ('0', '1');
 type character is (
  nul, soh, stx, etx, eot, enq, ack, bel,
  bs,  ht,  lf,  vt,  ff,  cr,  so,  si,
  dle, dc1, dc2, dc3, dc4, nak, syn, etb,
  can, em,  sub, esc, fsp, gsp, rsp, usp,

  ' ', '!', '"', '#', '$', '%', '&', ''',
  '(', ')', '*', '+', ',', '-', '.', '/',
  '0', '1', '2', '3', '4', '5', '6', '7',
  '8', '9', ':', ';', '<', '=', '>', '?',

  '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
  'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
  'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
  'X', 'Y', 'Z', '[', '\', ']', '^', '_',

  '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
  'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
  'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
  'x', 'y', 'z', '{', '|', '}', '~', del,

  c128, c129, c130, c131, c132, c133, c134, c135,
  c136, c137, c138, c139, c140, c141, c142, c143,
  c144, c145, c146, c147, c148, c149, c150, c151,
  c152, c153, c154, c155, c156, c157, c158, c159,

  -- the character code for 160 is there (NBSP),
  -- but prints as no char

  ' ', '?', '￠', '￡', '¤', '￥', '|', '§',
  '¨', '?', 'a', '?', '?', '­', '?', 'ˉ',
  '°', '±', '2', '3', '′', 'μ', '?', '·',
  '?', '1', 'o', '?', '?', '?', '?', '?',

  'à', 'á', '?', '?', '?', '?', '?', '?',
  'è', 'é', 'ê', '?', 'ì', 'í', '?', '?',
  'D', '?', 'ò', 'ó', '?', '?', '?', '×',
  '?', 'ù', 'ú', '?', 'ü', 'Y', 'T', '?',

  'à', 'á', 'a', '?', '?', '?', '?', '?',
  'è', 'é', 'ê', '?', 'ì', 'í', '?', '?',
  'e', '?', 'ò', 'ó', '?', '?', '?', '÷',
  '?', 'ù', 'ú', '?', 'ü', 'y', 't', '?' );

 type severity_level is (note, warning, error, failure);
 type integer is range -2147483648 to 2147483647;
 type real is range -1.0E308 to 1.0E308;
 type time is range -2147483647 to 2147483647
  units
   fs;
   ps = 1000 fs;
   ns = 1000 ps;
   us = 1000 ns;
   ms = 1000 us;
   sec = 1000 ms;
   min = 60 sec;
   hr = 60 min;
  end units;
 subtype delay_length is time range 0 fs to time'high;
 impure function now return delay_length;
 subtype natural is integer range 0 to integer'high;
 subtype positive is integer range 1 to integer'high;
 type string is array (positive range <>) of character;
 type bit_vector is array (natural range <>) of bit;
 type file_open_kind is (
  read_mode,
  write_mode,
  append_mode);
 type file_open_status is (
  open_ok,
  status_error,
  name_error,
  mode_error);
 attribute foreign : string;
end standard;

                         '-'   -- Don't care
                       );

STD_LOGIC system described above is a subtype of STD_ULOGIC. The latter
includes an extra logic value, ‘U’, which stands for unresolved. Thus, contrary to
STD_LOGIC, conflicting logic levels are not automatically resolved here, so output
wires should never be connected together directly. However, if two output wires are
never supposed to be connected together, this logic system can be used to detect
design errors.
BOOLEAN: True, False.
INTEGER: 32-bit integers (from 2,147,483,647 to t2,147,483,647).
NATURAL: Non-negative integers (from 0 to t2,147,483,647).
REAL: Real numbers ranging from 1.0E38 to t1.0E38. Not synthesizable.
Physical literals: Used to inform physical quantities, like time, voltage, etc. Useful
in simulations. Not synthesizable.
Character literals: Single ASCII character or a string of such characters. Not
synthesizable.
SIGNED and UNSIGNED: data types defined in the std_logic_arith package of
the ieee library. They have the appearance of STD_LOGIC_VECTOR, but accept
arithmetic operations, which are typical of INTEGER data types (SIGNED and
UNSIGNED will be discussed in detail in section 3.6).

x0 <= '0';                          -- bit, std_logic, or std_ulogic value '0'
x1 <= "00011111";            -- bit_vector, std_logic_vector,
                                        -- std_ulogic_vector, signed, or unsigned
x2 <= "0001_1111";         -- underscore allowed to ease visualization
x3 <= "101111"                 -- binary representation of decimal 47
x4 <= B"101111"              -- binary representation of decimal 47
x5 <= O"57"                      -- octal representation of decimal 47
x6 <= X"2F"                     -- hexadecimal representation of decimal 47
n <= 1200;                         -- integer
m <= 1_200;                       -- integer, underscore allowed
IF ready THEN...                -- Boolean, executed if ready="TRUE"
y <= 1.2E-5;                       -- real, not synthesizable
q <= d after 10 ns;               -- physical, not synthesizable