原创 PWM VHDL程序，双路互补输出,精度占空比可调

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity pwm is
 generic(N: integer :=8 );
 port(   clk : in std_logic;
   q : in std_logic_vector(N-1 downto 0);
   pwmout1 : out std_logic;
   pwmout2 : out std_logic
  );
end pwm;
architecture rtl of pwm is
 signal pwmout1_temp:std_logic;
 signal qtemp:std_logic_vector(N-1 downto 0);
begin
 pwmout1 <= pwmout1_temp;
 pwmout2 <= not pwmout1_temp;
 process(clk)
 begin
  if (clk'event and clk='1') then
  qtemp<=qtemp+1;
  end if;
 end process;
 process(clk)
 begin
  if (clk'event and clk='1') then
   if qtemp<q then
    pwmout1_temp<='1';
   else
    pwmout1_temp<='0';
   end if;
  end if;
 end process;
end rtl;

计算公式为f=fclk/(2^N);

f：目标频率即我们想要输出的的PWM频率

fclk：clk端输入频率，一般是接有源晶振；

这里的是N取8，2^8=256;1/256占空比可调；

如果N取10,2^10=1024;1/1024占空比可调；

q占空比是控制端，一般是接单片机或其他设备；