原创 VHDL 10进制加法器 进位输出 自动复位 可级联

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter10 is
 port( clk : in std_logic;
       aout : out std_logic_vector(3 downto 0);
       cout : out std_logic
      );
end;

architecture behav of counter10 is
signal cnt10 : std_logic_vector(3 downto 0):="0000";
begin
aout<=cnt10;
process(clk)
begin
 if clk'event and clk='1' then
 if cnt10="1001" then
  cnt10<="0000";
  cout<='1';
 else
  cnt10<=cnt10+1;
  cout<='0';
 end if;
 end if;
end process;
end;