原创 wishbone bus

摘 要<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

Wishbone总线标准是一种SOC片上系统IP核互连体系结构标准。它定义了一种IP核之间公共的逻辑接口，减轻了系统组件集成的难度，提高了系统组件的可重用性、可靠性和可移植性，加快了产品市场化的速度。Wishbone总线规范可用于软核、固核和硬核，对开发工具和目标硬件没有特殊要求，并且几乎兼容已有所有的综合工具，可以用多种硬件描述语言来实现。

首先介绍wishbone接口的相关知识，然后根据这一标准，用VerilogHDL硬件描述语言编写出能正确实现符合wishbone总线接口标准的电路代码，并仿真，综合，优化。

关键字： wishbone     片上系统     接口设计     IP核集成     VerilogHDL

Abstract

The wishbone is a standard for System-on-Chip (SOC) interconnection architecture. Its purpose is to foster design reuse by alleviating System-on-Chip integration problems. This is accomplished by creating a common interface between IP cores. This improves the portability and reliability of the system, and results in faster time-to-market for the end user. This specification can be used for soft core, firm core or hard core IP. This specification does not require the use of specific development tools or target hardware. Furthermore, it is fully compliant with virtually all logic synthesis tools and can be realized by many hardware description languages.

First some knowledge about the wishbone interface are introduced , then according to this specification , some codes which can realize its functions are composed with the language VerilogHDL.

keywords:  wishbone  SOC  interface design  IP integration  VerilogHDL