原创 Timing Closure Methodology for FPGA Design

2009-10-7 15:36 2264 0 分类: FPGA/CPLD
 

https://assets-stash.oss-cn-shanghai.aliyuncs.com/album/old-resources/2009/10/7/61b58ae7-95d5-4319-9746-af0acebb7605.rar" target=_blank>EARLY COMPILATION OF BLOCKS

 

1: 在设计之初就需要考虑好模块的划分,不要等到所有的模块都完成之后再编译,把功能最复杂的模块完成后马上编译,然后根据编译后的结果来定芯片的选择等等

2:尽量减少模块之间的信号连接数量,并且所有的输入输出信号都需要用寄存器来缓存,因为在采用增量编译设计方法的时候,在单独编译每个模块的时候无法知道他所连接的模块的情况,没有办法优化。

A common problem that prolongs the design cycle is waiting for code completion to compile the design. With this approach, issues are not detected until the end.

Compile your major blocks as soon as you can, even if your design is not complete.This allows you to identify coding styles that may not be appropriate for the chosen device. By doing this, you can also identify resource issues early in the design cycle.


You should minimize inter-block connections when creating design blocks. Register all inputs and outputs from each block to avoid critical timing paths crossing between module boundaries. If you use incremental compilation partitions, details of other partitions are not visible when the Quartus II software works on one of the partitions;therefore, optimization (or logic minimization) across partitions is not possible.

 

CODING STYLES

 

在写代码的时候需要考虑到代码最终会映射到FPGA的何种资源。比如,如果写的代码想要映射成为RAM,但是如果使用了同步或者异步来清空CELL的内容,或者对CELL进行初始化,那么最终可能映射不成RAM,因为实际的RAM不带有这种功能。

You might under utilize some of the available resources if you are not aware of your hardware resources. In general, do not use constructs that lack the equivalent hardware implementation available in the device. For example, your code might not be mapped to any of the available RAM blocks in the device if you infer RAM locations and use synchronous resets on RAM locations to clear the contents or to initialize the values. This is because the RAM locations in Altera devices do not has asynchronous or synchronous resets available for RAM cells. Instead, logic that models a memory with a reset is implemented in logic cells. Review your specifications to verify if having a known initial value in the RAMs is necessary for proper design function (most often it is not required). If RAM cells have to be initialized to certain known values (such as all 0’s), consider performing write cycles to the RAM immediately after power up.
You must consider hardware mapping when you code. Changes in the code can affect
the number of logic levels and the corresponding timing. Although the software
optimizes your design, unnecessary optimizations can affect software performance.
Editing the HDL can improve the quality of results.

 

HIGH FAN-OUT SIGNALS

 

当某个信号的扇出太大的时候,可能会造成有的ROUTING路径很长,造成时序问题。一个解决办法是把需要高扇出的信号复制出来多个(duplicated registers),这样的话,fitter在布局和走线的时候会考虑使用哪个等效的duplicated registers来走线。但是需要注意不要让quartus把duplicated registers优化掉


  • Put a synthesis attribute in the code to preserve the register, or turn off Remove Duplicate Registers in the register or hierarchy
  • Use the Assignment Editor to manually select the register you want to duplicate,and turn on duplication
  • Use the Assignment Editor to provide a Maximum Fan-out assignment. This
    creates as many duplicate registers as required, depending on the fan-out
  • Turn on physical synthesis and enable register duplication

Metastability

   这里所说的不稳定性指的是不同时钟域的信号在传递的过程中可能出现的不稳定状态,可能会导致状态机误跳转,或者状态不触发。ALTERA提供了METASTABILITY ADVISOR,可以用来分析这种不稳定。


Design Tips


*如果是setup time引起的时序问题,可以通过降低频率来解决;如果是hold time引起的,那么通过降频是解决不了的。


One reason for unexplained failures on a board could be timing requirements that were not specified while running static timing analysis. If these were caused by setup failures, you may be able to run the design at a rate slower than the intended frequency and verify your design. However, if failures exist because of hold violations that were not resolved, the design cannot function reliably at any frequency. Also,depending on the timing requirements that are not met, your design may operate correctly at certain temperatures or voltages, but fail at a different temperature or
voltage range.


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