原创 开关电源Layout LT1765

As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. For maximum effciency, switch rise and fall times are typically in the nanosecond range. To prevent noise both radiated and conducted, the high speed switching current path, shown in Figure 5, must be kept as short as possible. Shortening this path will also reduce the parasitic trace inductance of approximately 25nH/inch. At switch off, this parasitic inductance produces a flyback spike across the LT1765 switch. When operating at higher currents and input voltages, with poor layout, this spike can generate voltages across the LT1765 that may exceed its absolute maximum

rating. A ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise.The VC and FB components should be kept as far away as possible from the switch and boost nodes. The LT1765 pinout has been designed to aid in this. The ground for these components should be separated from the switch current path. Failure to do so will result in poor stability or subharmonic like oscillation.
Board layout also has a signi?  cant effect on thermal resistance. The exposed pad or GND pin is a continuous copper plate that runs under the LT1765 die. This is the best thermal path for heat out of the package as can be seen by the low θJC of the exposed pad package. Reduc-ing the thermal resistance from Pin 4 or exposed pad onto the board will reduce die temperature and increase the power capability of the LT1765. This is achieved by providing as much copper area as possible around this pin/pad. Also, having multiple solder ?  lled feedthroughs to a continuous copper plane under LT1765 will help in reducing thermal resistance. Ground plane is usually suitable for this purpose. In multilayer PCB designs, placing a ground plane next to the layer with the LT1765 will reduce thermal resistance to a minimum.