原创 Cyclone II FPGA External Memory Resources

 2009-8-24 16:21  2013 4 4 分类: FPGA/CPLD

http://www.altera.com.cn/technology/memory/devices/cyclone2/mem-cyclone2.html

Cyclone^? II FPGAs support a broad range of external memory interfaces, such as SDR SDRAM, DDR SDRAM, DDR2 SDRAM, and QDRII SRAM.

Memory Type	Maximum Data Rate (Per Pin)	Maximum Clock Frequency
*Table 1. Cyclone II Maximum Clock Rate Support for External Memory Interfaces*
DDR2 SDRAM	333 Mbps	167 MHz
DDR SDRAM	333 Mbps	167 MHz
QDRII SRAM	667 Mbps	167 MHz

Collateral	Description
Table 2. Cyclone II External Memory Resources
Start Here
AN 361: Interfacing DDR and DDR2 SDRAM With Cyclone II Devices (PDF)	Describes the interface architecture, signals, and timing analysis for DDR/DDR2 SDRAM memory.
Device Selection
Selecting the Right High-Speed Memory Technology for Your System (PDF)	Describes how to select the right memory for your application.
The Efficiency of the DDR and DDR2 SDRAM Controller Compiler (PDF)	Describes the terminologies such as bandwidth, efficiency, and read latency.
External Memory Interfaces (PDF)	Describes Cyclone^? II device internals such as DDR memory interface pins, DQS phase-shift circuitry, and DDR registers.
IP/Megafunction User Guides
DDR/DDR2 SDRAM Controller Compiler User Guide (PDF)	Describes the controller interface and also the design flow using SOPC Builder and the MegaWizard^? Plug-In Manager
IP MegaStore^TM	The web page links to different intellectual property (IP) cores provided by Altera and Altera's partners. The web page also allows you to search for an IP according to your interests.
Applications and Debug
AN 398: Using DDR/DDR2 SDRAM With SOPC Builder (PDF)	Describes the design flow for instantiating a DDR2 controller in SOPC Builder and verifying the read-and-write transactions using SignalTap^? II logic analyzer.
AN 392: Multiple DDR and DDR2 SDRAM Controllers On One Device (PDF)	Describes the design methodology for implementing multiple controllers in a single FPGA device.
AN 415: DDR and DDR2 SDRAM ECC Reference Design (PDF) ECC Reference Design Files	Describes how to use the ECC design block with DDR and DDR2 SDRAM controller.
AN 380: Test DDR or DDR2 SDRAM Interfaces on Hardware Using the Example Driver (PDF)	Describes the verification of an example design using functional and hardware simulation.
Timing Analysis
TimeQuest Timing Analyzer (PDF)	Learn about the features of the TimeQuest analyzer and how to constrain your design with SDC commands.
TimeQuest Resources	This page provides links to resources for you to learn more about the TimeQuest analyzer.
Models and Board Design Guidelines
Board Design Guidelines Solution Center	The web page provides you with board design-related resources for Altera^? devices. Its goal is to help you implement successful high-speed PCBs that integrate device(s) and other elements.
HSPICE Models	Web page listing of all the HSPICE models for Altera devices.
IBIS Models	Web page listing of all the IBIS models for Altera devices.
Kits and Boards
Nios II Development Kit, Cyclone II Edition (2C35)	Altera's Nios^? II Development Kit, Cyclone II Edition provides a complete development environment, including everything hardware and software designers need for system-level designs and testing the external memory interface.
PCI Development Kit, Cyclone II Edition	Altera's PCI Development Kit, Cyclone II Edition delivers a complete PCI-based development platform for design engineers that includes an external DDR2 memory for testing the external memory interface.
Video Development Kit, Cyclone II Edition	The Video Development Kit, Cyclone II Edition delivers a complete video development environment for design engineers that includes an external DDR2 memory for testing the external memory interface.