原创 数码管动态显示的VHDL程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity led is
port(
clkfast:in std_logic;
clkslow:in std_logic;
sel:out std_logic_vector(2 downto 0);
data:out std_logic_vector(7 downto 0)

);
end led;

architecture bh of led is
signal cnt1,cnt2:integer range 0 to 9;
signal carry:std_logic;
signal q:std_logic_vector(1 downto 0);
signal selq:std_logic_vector(2 downto 0);
signal dataq:std_logic_vector(3 downto 0);
signal dataout:std_logic_vector(7 downto 0);
begin

sel<=selq;
data<=dataout;
process(clkslow)
begin
if rising_edge(clkslow) then

          if cnt1=9 then cnt1<=1;carry<='1';
          else
           cnt1<=cnt1+1;
           carry<='0';

          end if;
end if;
end process;

process(carry)
begin
if carry'event and carry='1'
     then cnt2<=cnt2+1;
end if;
end process;
 

process(clkfast)
begin
if rising_edge(clkfast)then
    if q="11" then
         q<="00";
    else
         q<=q+1;
    end if;
end if;
end process;

process(q)
begin
case q is
when "00"=>selq<="000";
when "01"=>selq<="001";
when others=>null;
end case;
end process;

process(selq)
begin
case selq is
when "000"=>dataq<=conv_std_logic_vector(cnt1,4);
when "001"=>dataq<=conv_std_logic_vector(cnt2,4);
when others=>null;
end case;
end process;

process(dataq)
begin
case dataq is
when "0000"=>dataout<="00000110";
when "0001"=>dataout<="01011011";
when "0010"=>dataout<="01001111";
when "0011"=>dataout<="01100110";
when "0100"=>dataout<="01101101";
when "0101"=>dataout<="01111101";
when "0110"=>dataout<="00100111";
when "0111"=>dataout<="01111111";
when "1000"=>dataout<="01101111";
when others=>null;
end case;
end process;
end bh;