一、想法
七段数码管与二进制计数信号的同时计数，每秒一次。
二、HDL描述
counter_SEG7.v / Verilog
/*
(C) http://blog.ednchina.com/2006TX_yafeng
Filename : counter_SEG7.v
Compiler : Quartus II 8.0
Device : EP2C20F484C7 (Altera DE1)
Description : 示例怎样生成一个计秒七段数码管
Release : 9/5/2008 1.0
*/
Compiler : Quartus II 8.0
Device : EP2C20F484C7 (Altera DE1)
Description : 示例怎样生成一个计秒七段数码管
Release : 9/5/2008 1.0
*/
module counter_SEG7 (
output [6:0] HEX0, // 七段数码管 0
input CLOCK_50, // 板载50 MHz时钟
input wire [0:0] KEY // 按钮0
);
wire clk_1_Hz;
reg [15:0] cnt;
// 例化分频器，得到1 Hz时钟
divider_by_50M u0 (
.o_clk(clk_1_Hz),
.rst_n(KEY),
.i_clk(CLOCK_50)
);
divider_by_50M u0 (
.o_clk(clk_1_Hz),
.rst_n(KEY),
.i_clk(CLOCK_50)
);
// 获取按秒计数单元
always @ (posedge clk_1_Hz, negedge KEY)
begin
if (!KEY)
cnt <= 0;
else
begin
if (cnt == 15) // 1'hf
cnt <= 0;
else
cnt <= cnt + 1'b1;
end
end
always @ (posedge clk_1_Hz, negedge KEY)
begin
if (!KEY)
cnt <= 0;
else
begin
if (cnt == 15) // 1'hf
cnt <= 0;
else
cnt <= cnt + 1'b1;
end
end
// 例化七段数码管译码器
SEG7_LUT u1 (
.oSEG0(HEX0),
.iDIG(cnt[3:0])
);
SEG7_LUT u1 (
.oSEG0(HEX0),
.iDIG(cnt[3:0])
);
endmodule
divider_by_50M.v / Verilog
module divider_by_50M (
output reg o_clk,
input rst_n,
input i_clk
);
parameter N = 50_000_000;
output reg o_clk,
input rst_n,
input i_clk
);
parameter N = 50_000_000;
parameter M = 24_999_999; // M=(N/2)-1
reg [25:0] cnt;
always @ (posedge i_clk, negedge rst_n)
begin
if (!rst_n)
cnt <= 0;
else
begin
if (cnt == N-1)
cnt <= 0;
else
cnt <= cnt + 26'b1;
end
end
always @ (posedge i_clk, negedge rst_n)
begin
if (!rst_n)
cnt <= 0;
else
begin
if (cnt == N-1)
cnt <= 0;
else
cnt <= cnt + 26'b1;
end
end
always @ (posedge i_clk, negedge rst_n)
begin
if (!rst_n)
o_clk <= 0;
else
begin
if (cnt <= M)
o_clk <= 1;
else
o_clk <= 0;
end
end
endmodule
begin
if (!rst_n)
o_clk <= 0;
else
begin
if (cnt <= M)
o_clk <= 1;
else
o_clk <= 0;
end
end
endmodule
SEG7_LUT.v / Verilog
module SEG7_LUT (
output reg [6:0] oSEG,
input [3:0] iDIG
);
output reg [6:0] oSEG,
input [3:0] iDIG
);
always @ (iDIG)
begin
case (iDIG)
4'h1: oSEG = 7'b1111001; // ---t---
4'h2: oSEG = 7'b0100100; // | |
4'h3: oSEG = 7'b0110000; // lt rt
4'h4: oSEG = 7'b0011001; // | |
4'h5: oSEG = 7'b0010010; // ---m---
4'h6: oSEG = 7'b0000010; // | |
4'h7: oSEG = 7'b1111000; // lb rb
4'h8: oSEG = 7'b0000000; // | |
4'h9: oSEG = 7'b0011000; // ---b---
4'ha: oSEG = 7'b0001000;
4'hb: oSEG = 7'b0000011;
4'hc: oSEG = 7'b1000110;
4'hd: oSEG = 7'b0100001;
4'he: oSEG = 7'b0000110;
4'hf: oSEG = 7'b0001110;
default: oSEG = 7'b1000000;
endcase
end
begin
case (iDIG)
4'h1: oSEG = 7'b1111001; // ---t---
4'h2: oSEG = 7'b0100100; // | |
4'h3: oSEG = 7'b0110000; // lt rt
4'h4: oSEG = 7'b0011001; // | |
4'h5: oSEG = 7'b0010010; // ---m---
4'h6: oSEG = 7'b0000010; // | |
4'h7: oSEG = 7'b1111000; // lb rb
4'h8: oSEG = 7'b0000000; // | |
4'h9: oSEG = 7'b0011000; // ---b---
4'ha: oSEG = 7'b0001000;
4'hb: oSEG = 7'b0000011;
4'hc: oSEG = 7'b1000110;
4'hd: oSEG = 7'b0100001;
4'he: oSEG = 7'b0000110;
4'hf: oSEG = 7'b0001110;
default: oSEG = 7'b1000000;
endcase
end
endmodule
三、另见
- 上一篇： 计秒LED.(Verilog)
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