原创 PicoBlaze_RS232_StrataFlash实验分析报告一（硬件模块对应VHDL分析）

系统硬件结构(图片复制不过来，具体见下载文档)

<?xml:namespace prefix = v ns = "urn:schemas-microsoft-com:vml" /><?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />VHDL程序结构：

       下面逐个分析硬件的组成和VHDL代码的关系。

       1:首先是KCPSM3与ROM的连接：

代码如下： 主要就是指令的读取：地址线，数据线和复位

 processor: kcpsm3

    port map(      address => address,

               instruction => instruction,

                   port_id => port_id,

              write_strobe => write_strobe,

                  out_port => out_port,

               read_strobe => read_strobe,

                   in_port => in_port,

                 interrupt => interrupt,

             interrupt_ack => interrupt_ack,

                     reset => kcpsm3_reset,

                       clk => clk);

  program_rom: progctrl

    port map(      address => address,

               instruction => instruction,

                proc_reset => kcpsm3_reset,

                       clk => clk);

2：关于KCPSM的INPUT

如上图所示：主要通过一个三路复用器来选择输入由port_id(1 downto 0)选择。一路是状态，一路是串口送来的数据，一路是flash读取的数据。代码如下{通过case语句}：

input_ports: process(clk)

  begin

    if clk'event and clk='1' then

      case port_id(1 downto 0) is

        -- read status signals at address 00 hex

        when "00" =>    in_port <= status_port; 一路是状态

        -- read UART receive data at address 01 hex

        when "01" =>    in_port <= rx_data; 一路是串口送来的数据

        -- read StrataFLASH memory data at address 02 hex

        when "10" =>    in_port <= strataflash_d; flash读取的数据

        -- Don't care used for all other addresses to ensure minimum logic implementation

        when others =>    in_port <= "XXXXXXXX"; 

      -- Form read strobe for UART receiver FIFO buffer at address 01 hex.

      -- The fact that the read strobe will occur after the actual data is read by

      -- the KCPSM3 is acceptable because it is really means 'I have read you'!

      if (read_strobe='1' and port_id(1 downto 0)="01") then  ------ read_strobe='1'表示有数据写入处理器

        read_from_uart <= '1';    从UART的接收fifo读取数据，读有效。然后下一个时钟新数据写入rx_data，自动输出给in_port

       else

        read_from_uart <= '0';

      end if;

    end if;

  end process input_ports;

注意：status_port <= strataflash_sts & '0' & rx_full & rx_half_full & rx_data_present & tx_full & tx_half_full & tx_data_present;(有多个bit组合而成的主要表示各个部分的状态)

3：关于KCPSM的OUTPUT

通过port_id选择输出，输出有flash的数据，地址，还有控制信号。

  output_ports: process(clk)

  begin

    if clk'event and clk='1' then

      if write_strobe='1' then

        -- The 24-bit address to the StrataFLASH memory requires 3 ports.

        -- Address [23:16] at port 80 hex

        if port_id(7)='1' then

          strataflash_a(23 downto 16) <= out_port;

        end if;

        -- Address [15:8] at port 40 hex

        if port_id(6)='1' then

          strataflash_a(15 downto 8) <= out_port;

        end if;

        -- Address [7:0] at port 20 hex

        if port_id(5)='1' then

          strataflash_a(7 downto 0) <= out_port;

        end if;

        -- Data to be written to StrataFlash at port 10 hex

        if port_id(4)='1' then

          write_data <= out_port;

        end if;

        -- StrataFlash control signals at port 08 hex

        if port_id(3)='1' then  ---------控制信号  具体的操作件软件汇编操作

          strataflash_read <= out_port(0);  --Active High and used to control data bus direction and OE

          strataflash_ce <= out_port(1);    --Active Low StrataFLASH device enable

          strataflash_we <= out_port(2);    --Active Low StrataFLASH write enable

        end if;

      end if;

    end if;

  end process output_ports;

4：串口的软核

   4.1：发送方向的综合图

实际模块组成，及信号

以上是发送uart的组成：一个fifo和一个并串转换（把8bit的并行数据转换成为串行的8bit）。其中Tx_complete表示在发送完串行数据以后那么就可以重新接收fifo的数据，即 使fifo的读有效。

Data_present表示整个模块正在发送数据。模块仿真如下：

TX_buffer的操作：

4.2 接收方向的偶综合图

实际的模块信号图：

      其他略

5：波特率的产生：

  --

  -- Set baud rate to 115200 for the UART communications

  -- Requires en_16_x_baud to be 1843200Hz which is a single cycle pulse every 27 cycles at 50MHz

  --

  baud_timer: process(clk)

  begin

    if clk'event and clk='1' then

      if baud_count=26 then

         baud_count <= 0;

         en_16_x_baud <= '1';

       else

         baud_count <= baud_count + 1;

         en_16_x_baud <= '0';

      end if;

    end if;

  end process baud_timer;

6：其他信号的初始化（硬件完成）

----------------------------------------------------------------------------------------------------------------------------------

  -- Disable unused components 

  ----------------------------------------------------------------------------------------------------------------------------------

  --

  -- Although the LCD display only uses pins shared with the StrataFLASH upper data bits [15:8] the following signals ensure that no possible conflict can occur when experimenting with the StrataFLASH memory beyond the design currently presented.

  --

  lcd_rw <= '0';     --Always writing to display prevents display driving out.

  lcd_e  <= '0';     --No enable pulses to the display ensures that display contents do not change.

  --

  --

  -- The LSB of the data bus to and from the StrataFLASH device (D0) is connected to many components.

  -- This occurs because the board provides multiple ways to configure the Spartan-3E device and  

  -- consequently all these use the configuration DIN pin. Since one of these configuration options is SPI memory, the board also implements an SPI bus to which further devices are connected.The following signals ensure that additional connections to 'D0' can not cause any conflict with access to the StrataFLASH device.

  --

  platformflash_oe <= '0';    --Disable (reset) Platform FLASH device used in master serial configuration.

  spi_rom_cs <= '1';          --Disable SPI FLASH device used in SPI configuration.

  spi_adc_conv <= '0';        --Prevent SPI based A/D converter from generating sample data.

  spi_dac_cs <= '1';          --Disable SPI based D/A converter interface.

  strataflash_byte <= '0';-- Set 8-bit mode of operation for StrataFLASH memory