原创 IO地址译码设计--Protel99SE自带CUPL语言设计

Name        PLDDesign1           ;
Partno      1                    ;
Revision    1                    ;
Date        3/12/02              ;
Designer    HotPower             ;
Company     Protel International ;
Assembly    I/O read/write       ;
Location                         ;
Device      g16v8                ;
Format      j                    ;

/*********************************************************************/
/* This PLD design (Revision 1) created on 3/12/02                   */
/*      for                   Protel International                   */
/*      and is stored as      PLDDesign                              */
/*********************************************************************/

/** Inputs  **/
Pin 2   =  a0;
Pin 3   =  a1;
Pin 4   =  a2;
Pin 5   =  a3;
Pin 6   =  a4;
Pin 7   =  a5;
Pin 8   =  a6;
Pin 9   =  a7;
Pin 12  =  iord;
Pin 13  =  iowr;

/** Outputs **/
Pin 19  =  buffen;

/** Declarations and Intermediate Variables  **/
field addr = [a7..0];
ioreq     = !iord # !iowr;

/** Logic Equations **/
!buffen     = ioreq & addr: [10..12];