原创 83优先编码--Protel99SE自带CUPL语言设计

Name        PLDDesign7           ;
Partno                           ;
Revision    1                    ;
Date        3/13/02              ;
Designer    HotPower                  ;
Company     Protel International ;
Assembly                         ;
Location                         ;
Device      g16v8                ;
Format      j                    ;

/*********************************************************************/
/* This PLD design (Revision 1) created on 3/13/02                   */
/*      for                   Protel International                   */
/*      and is stored as      PLDDesign                              */
/*********************************************************************/

/** Inputs  **/
Pin[1, 11, 10, 20] = [ei, oe, GND, VCC];
Pin[2..9] = [d0..7];

/** Outputs **/
Pin[15..17] = [y0..2];
Pin[19] = gs;

/** Declarations and Intermediate Variables  **/
fld flds7 = [d7..0];
fld flds6 = [d6..0];
fld flds5 = [d5..0];
fld flds4 = [d4..0];
fld flds3 = [d3..0];
fld flds2 = [d2..0];
fld flds1 = [d1..0];
fld flds0 = [d0..0];

/** Logic Equations **/
y0 = (!ei & !oe) &
     ((d0 & !d1) #
     ( d0 & d1 & d2 & !d3) #
     ( d0 & d1 & d2 &  d3 & d4 & !d5) #
     ( d0 & d1 & d2 &  d3 & d4 &  d5 & d6 & !d7) #
     ( d0 & d1 & d2 &  d3 & d4 &  d5 & d6 &  d7));

y1 = (!ei & !oe) &
     ([d2..0]: 'b'011
   #  [d2..0]:& & !d3
   #  !d6 & [d5..0]:&
   #  [d7..0]: 'b'01111111
   #  [d7..0]: 'b'11111111); /** fids7:& **/

y2 = (!ei & !oe) &
     (flds4: 'b'01111    #
      flds5: 'b'011111   #
      flds6: 'b'0111111  #
      flds7: 'b'01111111 #
      flds7: 'b'11111111); /** fids7:& **/

gs = ei # oe # flds7:&;