原创 这算不算用verilog实现了uart

可以将超级终端发出的数据返回，但太简单了，能算是用verilog实现了uart吗？

`timescale 1ns / 1ps

//功能：接收超级终端发过来的字符，并将其返回
//用状态机实现，共有3个状态空闲、接收、发射
module uart_ht (clk, rst_n, uart_tx, uart_rx);

input   clk;          //主时钟50Mhz
input   rst_n;        //低电平复位
input   uart_rx;

output  uart_tx;      //uart发送

parameter  IDLE="3"'b001,
           UART_RX=3'b010,
           UART_TX=3'b100;

//---------------------------------------------------
reg [12:0] cnt1;  //波特率的分频器
always @ ( posedge clk or negedge rst_n )
  if( !rst_n )  cnt1<=1'b0;
  else if(uart_clken)
       begin
       if( cnt1==13'h1458 ) cnt1<=1'b0;//波特率是9600
       else cnt1<=cnt1+1'b1;
       end 
       else    cnt1<=1'b0;

//---------------------------------------------------
reg [3:0] cnt2;
always @ ( posedge clk or negedge rst_n )
  if ( !rst_n ) cnt2<=1'b0;
  else if( uart_clken )
       begin 
       if (cnt2==4'ha) cnt2<=1'b0;//8个数据位一个停止位，
       else if(cnt1==13'h1458) cnt2<=cnt2+1'b1;
       end
       else  cnt2<=1'b0;

//---------------------------------------------------
reg uart_tx_r;
always @ ( posedge clk or negedge rst_n )
   if ( !rst_n )  uart_tx_r=1'b1;
   else  if( state==UART_TX )
         begin
         if(cnt1==13'h1)
         case (cnt2)
         4'b0000: uart_tx_r<=0;
         4'b0001: uart_tx_r<=uart_data[0];
         4'b0010: uart_tx_r<=uart_data[1];
         4'b0011: uart_tx_r<=uart_data[2];
         4'b0100: uart_tx_r<=uart_data[3];
         4'b0101: uart_tx_r<=uart_data[4];
         4'b0110: uart_tx_r<=uart_data[5];
         4'b0111: uart_tx_r<=uart_data[6];
         4'b1000: uart_tx_r<=uart_data[7];
         4'b1001: uart_tx_r<=1;
         default: ;
         endcase
         end
         else uart_tx_r<=1'b1;

assign uart_tx=uart_tx_r;

reg uart_clken;
always @ ( posedge clk or negedge rst_n )
if(!rst_n)  uart_clken<=1'b0;
else if(state==IDLE) uart_clken<=1'b0;
     else uart_clken<=1'b1;

//从tx到rx应该有个数据中转站        
reg [2:0] state;
always @ ( posedge clk or negedge rst_n )
     if( !rst_n ) state<=IDLE;
     else case(state)
          IDLE    : if(!uart_rx)      state<=UART_RX;
          UART_RX : if(cnt2==4'ha)   state<=UART_TX;
          UART_TX : if(cnt2==4'ha)   state<=IDLE;
          default : state<=IDLE;
          endcase

reg[7:0] uart_data;
//下面这段代码是要将接收到的数据锁存起来
always @ ( posedge clk or negedge rst_n )
   if(!rst_n)  uart_data<=1'b1;
   else if(state==UART_RX)
        begin
        if(cnt1==13'h0500)
        case (cnt2)
        4'b0000: ;
        4'b0001: uart_data[0]<=uart_rx;
        4'b0010: uart_data[1]<=uart_rx;
        4'b0011: uart_data[2]<=uart_rx;
        4'b0100: uart_data[3]<=uart_rx;
        4'b0101: uart_data[4]<=uart_rx;
        4'b0110: uart_data[5]<=uart_rx;
        4'b0111: uart_data[6]<=uart_rx;
        4'b1000: uart_data[7]<=uart_rx;
        4'b1001: ;
        default: ;
        endcase
        end

endmodule