原创 S3C2440原理图中需要注意的几个配置选项

S3C2440原理图中需要注意的几个配置选项

OM[1:0] sets S3C2440A in the TEST mode, which is used only at
fabrication. Also, it determines the bus width of nGCS0. The pull-up/down
resistor determines the logic level during RESET cycle.

00: Nand-boot           01: 16-bit        10: 32-bit          11: Test mode

OM[3:2]
determines how the clock is made.

OM[3:2] = 00b, Crystal is used for MPLL CLK source and UPLL
CLK source.

OM[3:2] = 01b, Crystal
is used for MPLL CLK source and EXTCLK is used for UPLL CLK source.

OM[3:2] = 10b, EXTCLK is used for MPLL CLK
source and Crystal
is used for UPLL CLK source.

OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source.

OM[3:2] is used to determine a test mode
when OM[1:0] is 11.

一般原理图中选择OM[3:2]=00

NCON （Nand flash configuration）

If NAND flash controller isn’t used, it has to be pull-up. (VDDMOP)  

OM[1:0] = 00: Enable NAND flash memory boot

The WP pin provides inadvertent write/erase protection during power
transitions. The internal high voltage generator is reset when the WP pin is
active low.

WP pin provides
hard-ware  protection  and 
is  recommended  to 
be  kept  at  Vil
during  power-up  and 
power-down.

/WP接高电平允许擦除和写入，接低电平禁止擦除和写入。