原创 时钟边沿检测

在设计中有时为了利用两个不同频率的时钟脉冲时，为了区分两个脉冲的边沿触发，可以采用时钟边沿检测的方法实现，代码如下：

module edge_detect(
                 clk,
                 rst_n,
                 data_in,
                 raising_edge_detected,                     //上升沿检测
                 falling_edge_detected,                     //下降沿检测
                 double_edge_detected                    //双边沿检测
                 );
                             
input         clk;                 
input         rst_n;    
input         data_in;         
output        raising_edge_detected;
output        falling_edge_detected;
output        double_edge_detected;
wire          raising_edge_detected;
wire          falling_edge_detected;
wire          double_edge_detected;

reg           data_in_d1;                          //定义中间变量1
reg           data_in_d2;                          //定义中间变量2

always @(posedge clk or negedge rst_n)
begin
    if (rst_n == 1'b0)
        begin
            data_in_d1 <= 1'b0;
            data_in_d2 <= 1'b0;
        end
    else
        begin                 
            data_in_d1 <= data_in;
            data_in_d2 <= data_in_d1;
        end
end       

assign raising_edge_detected = data_in_d1 & ~data_in_d2;                  // 上升沿检测输出
assign falling_edge_detected = ~data_in_d1 & data_in_d2;                  //下降沿检测输出
assign double_edge_detected = data_in_d1 ^ data_in_d2;                   //双边沿检测输出

endmodule