原创 fpga

 2009-3-30 15:40  1868 2 2 分类: FPGA/CPLD

循环彩灯8路

library ieee ;

use ieee.std_logic_1164.all;

entity lamp is

port (nrst : in std_logic; --negative

shift_direction:in std_logic;--'1' for right ; '0' for left

clk:in std_logic;

Q : out std_logic_vector(7 downto 0) --controll 8 led lamp

);

end lamp;

architecture lamp of lamp is

signal temp : std_logic_vector(7 downto 0);

begin

process(clk,nrst,shift_direction)

begin

if nrst='0' then

temp(7 downto 0) <="10000000";

elsif clk'event and clk = '1' then

if shift_direction = '1' then

temp(7 downto 0) <= temp(0) & temp(7 downto 1) ;

else

temp(7 downto 0) <= temp(6 downto 0) & temp(7);

end if;

q(7 downto 0)<=temp(7 downto 0);

end process;

end lamp;

十进制计数器

发表于 2008/8/19 13:17:11

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*************************
ENTITY counter10 is
           PORT(
                  CP:IN Std_Logic;
                  Qout: OUT STD_LOGIC_VECTOR( 3 DOWNTO 0)
               );
END counter10;
--***************************
ARCHITECTURE demux4_behave OF counter10 IS
SIGNAL RST:STD_LOGIC;
SIGNAL QN:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
     proceSS(CP,RST)
     BEGIN
             IF RST='1'THEN
                  QN<="0000";
             ELSIF CP'EVENT AND CP='1'THEN
                  QN<=QN+1;
             END IF;
    END PROCESS;
    RST<='1'WHEN QN="10" ELSE
         '0';
    Qout<=QN;
END demux4_behave;

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