module LedWater(clk,rst_n,ledout);
input clk,rst_n;
output[5:0] ledout;
reg [5:0] ledout;
reg [25:0] count;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
count<=0;
else
count<=count+1'b1;
end
always @(posedge clk or negedge rst_n)
begin
case (count[25:22])
0: ledout<=6'b11_1110;
1: ledout<=6'b11_1100;
2: ledout<=6'b11_1000;
3: ledout<=6'b11_0000;
4: ledout<=6'b10_0000;
5: ledout<=6'b00_0000;
6: ledout<=6'b01_1111;
7: ledout<=6'b00_1111;
8: ledout<=6'b00_0111;
9: ledout<=6'b00_0011;
10:ledout<=6'b00_0001;
11:ledout<=6'b00_0000;
default:ledout<=6'b10_1010;
endcase
end
endmodule
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