原创 Microblaze LMB Bram Interface

pcores\lmb_bram_interface_v1_00_a\hdl\vhdl\lmb_bram_interface.vhd

library ieee;
use ieee.std_logic_1164.all;

entity lmb_bram_interface is
  generic (
    C_LMB_AWIDTH : integer                   := 32;
    C_LMB_DWIDTH : integer                   := 32
    );
  port (
    -- ports to BRAM bus
    IN_BRAM_Rst_A  : in  std_logic;
    IN_BRAM_Clk_A  : in  std_logic;
    IN_BRAM_Addr_A : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
    IN_BRAM_EN_A   : in  std_logic;
    IN_BRAM_WEN_A  : in  std_logic_vector(0 to C_LMB_DWIDTH/8-1);
    IN_BRAM_Dout_A : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
    IN_BRAM_Din_A  : out std_logic_vector(0 to C_LMB_DWIDTH-1);

    -- ports to external interface
    BRAM_Rst  : out std_logic;
    BRAM_Clk  : out std_logic;
    BRAM_Addr : out std_logic_vector(0 to C_LMB_AWIDTH-1);
    BRAM_EN   : out std_logic;
    BRAM_WEN  : out std_logic_vector(0 to C_LMB_DWIDTH/8-1);
    BRAM_Dout : out std_logic_vector(0 to C_LMB_DWIDTH-1);
    BRAM_Din  : in  std_logic_vector(0 to C_LMB_DWIDTH-1)
    );
end entity lmb_bram_interface;

architecture imp of lmb_bram_interface is

begin  -- architecture IMP

  BRAM_Rst    <= IN_BRAM_Rst_A;
  BRAM_Clk    <= IN_BRAM_Clk_A;
  BRAM_Addr   <= IN_BRAM_Addr_A;
  BRAM_EN     <= IN_BRAM_EN_A;
  BRAM_WEN    <= IN_BRAM_WEN_A;
  BRAM_Dout   <= IN_BRAM_Dout_A;
  IN_BRAM_Din_A <= BRAM_Din;
 
end architecture imp;

pcores\lmb_bram_interface_v1_00_a\data\lmb_bram_interface_v2_1_0.mpd

BEGIN lmb_bram_interface

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION STYLE = HDL
OPTION DESC = LMB BRAM Interface
OPTION LONG_DESC = Allows the LMB Block RAM interface to be mapped out external
OPTION ARCH_SUPPORT_MAP = (aspartan3=PREFERRED, spartan3=PREFERRED, spartan3an=PREFERRED, spartan3a=PREFERRED, spartan3e=PREFERRED, spartan3adsp=PREFERRED, virtex4lx=PREFERRED, virtex4sx=PREFERRED, virtex4fx=PREFERRED, virtex5lx=PREFERRED, virtex5sx=PREFERRED, virtex5fx=PREFERRED, aspartan3e=PREFERRED, aspartan3a=PREFERRED, aspartan3adsp=PREFERRED, qvirtex4lx=PREFERRED, qvirtex4sx=PREFERRED, qvirtex4fx=PREFERRED, qrvirtex4lx=PREFERRED, qrvirtex4sx=PREFERRED, qrvirtex4fx=PREFERRED, spartan6t=EARLY_ACCESS, spartan6=EARLY_ACCESS, virtex6lx=EARLY_ACCESS, virtex6sx=EARLY_ACCESS, virtex6cx=EARLY_ACCESS)

## Bus Interfaces
BUS_INTERFACE BUS = BRAM_PORT, BUS_STD = XIL_BRAM, BUS_TYPE = TARGET

## Generics for VHDL or Parameters for Verilog
PARAMETER C_LMB_AWIDTH = 32, DT = INTEGER
PARAMETER C_LMB_DWIDTH = 32, DT = INTEGER

## Ports
PORT IN_BRAM_Rst_A = BRAM_Rst, DIR = I, BUS = BRAM_PORT
PORT IN_BRAM_Clk_A = BRAM_Clk, DIR = I, BUS = BRAM_PORT
PORT IN_BRAM_Addr_A = BRAM_Addr, DIR = I, VEC = [0C_LMB_AWIDTH-1)], BUS = BRAM_PORT
PORT IN_BRAM_EN_A = BRAM_EN, DIR = I, BUS = BRAM_PORT
PORT IN_BRAM_WEN_A = BRAM_WEN, DIR = I, VEC = [0(C_LMB_DWIDTH/8)-1)], BUS = BRAM_PORT
PORT IN_BRAM_Dout_A = BRAM_Dout, DIR = I, VEC = [0C_LMB_DWIDTH-1)], BUS = BRAM_PORT
PORT IN_BRAM_Din_A = BRAM_Din, DIR = O, VEC = [0C_LMB_DWIDTH-1)], BUS = BRAM_PORT
PORT BRAM_Rst = "", DIR = O
PORT BRAM_Clk = "", DIR = O
PORT BRAM_Addr = "", DIR = O, VEC = [0C_LMB_AWIDTH-1)]
PORT BRAM_EN = "", DIR = O
PORT BRAM_WEN = "", DIR = O, VEC = [0(C_LMB_DWIDTH/8)-1)]
PORT BRAM_Dout = "", DIR = O, VEC = [0C_LMB_DWIDTH-1)]
PORT BRAM_Din = "", DIR = I, VEC = [0C_LMB_DWIDTH-1)]

END

pcores\lmb_bram_interface_v1_00_a\data\lmb_bram_interface_v2_1_0.pao

################################################################################
##
## Copyright (c) 2003 Xilinx Inc.  All rights reserved. 
##
## lmb_bram_interface.pao
##
## Peripheral Analyze Order
##
################################################################################

lib lmb_bram_interface_v1_00_a lmb_bram_interface vhdl