原创 自动售饮料机【很笨的方法,只卖一种饮料】

2009-11-26 19:55 3143 7 7 分类: FPGA/CPLD

module salemachine(one,two,five,take,clk,rst,seg,cs);
    input one,two,five,rst,clk;
    output take,cs;
    output [7:0] seg;
    parameter st0=0,st1=1,st2=2,st3=3,st4=4;
    reg take;
    reg [2:0]state;
    reg [27:0] count;
    reg [7:0] seg;
    assign cs =0;
    always@(posedge clk)
     begin
 count<=count+1;
 if(!rst)
   begin
   state<=0;
   take<=1;
   count<=0;
   seg<=8'b11111100;
   end
  else if(count==25000000)
    begin 
    count<=0;
   case(state)
   st0:begin
    seg<=8'b11111100;
    if(!one) begin state<=st1;seg<=8'b01100000;end
    else if(!two) begin state<=st2;seg<=8'b11011010;end
     else if(!five) take<=0;
      else take<=1;
    end


   st1: begin
    seg<=8'b01100000;
    if(!one) begin state<=st2;seg<=8'b11011010;end
    else if(!two) begin state<=st3;seg<=8'b11110010;end
     else if(!five) take<=0;
     else take<=1;
    end


   st2:begin
    seg<=8'b11011010;
       if(!one) begin state<=st3;seg<=8'b11110010;end
    else if(!two) begin state<=st4;seg<=8'b01100110;end
     else if(!five) take<=0;
      else take<=1;
    end


   st3:begin
    seg<=8'b11110010;
    if(!one) begin state<=st4;seg<=8'b01100110;end
    else if(!two) begin state<=st0;take<=0;end
     else if(!five) take<=0;
      else take<=1;
    end


   st4:begin
    seg<=8'b01100110;
    if(!one) begin take<=0;state<=st0;end
     else if(!two) begin take<=0;state<=st1;end
      else if(!five) take<=0;
      else take<=1;
    end
   endcase
   end
 end
endmodule

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