原创 Dt/Dv (Delta) Input Transition Rise or Fall Rate

Dt/Dv (Delta) Input Transition Rise or Fall Rate

JEDEC – no definition offered

TI – The rate of change of the input voltage waveform during a logic transition (low-to-high or high-to-low).

To avoid output-waveform abnormalities, input voltage transitions should be within the range set forth in the recommended operating conditions.

Customers often place external capacitors on a trace to ensure the driver does not switch rapidly from one logic state to another. This is sometimes done to prevent unwanted overshoot and undershoot voltage conditions that could cause ringing and degrade signal integrity, or in switch debounce circuits. However, this could cause problems at t input; therefore, TI provides input transition rise or fall rates. The problem may not arise due to external capacitive loading, however, but may be the result of choosing a device with a weak driver. In either case, the end result is a voltage waveform that is too slow for the device.

Slow transition rates wreak havoc on CMOS inputs because a slowly changing input voltage will induce a large amount of current from the power supply to ground. This phenomenon is known as through current. Through currents are normal ac transient currents, but when they are sustained indefinitely–as are those caused by slow input transition rates–the device will not perform as expected, and its output voltage may oscillate or, even worse, damage the device.

This surge of current, if large enough, will disturb the ground reference because of the inductive nature of the package [V = L × (di/dt)] and produce a positive-going glitch on the ground reference. The glitch may, in turn, reduce the relative magnitude, causing the output node of the input inverter to switch states. Ultimately, this erroneous data propagates to the output of the device, thereby causing oscillations. The more inputs that are being switched in the same manner, the worse this condition becomes, as more current is being forced into ground during a short time. TI data sheets specify the slowest input transition rate to avoid this problem. For additional information, refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

Helpful Hint:

If you must supply a slowly changing voltage to the input of a logic device, select a device that has Schmitt-trigger inputs. These inputs have been specifically designed to tolerate slow edges. An example of such a device in the LVC family is the SN74LVC14.

看来，对慢信号进入逻辑电路前，还是得加个施密特触发器或选取带施密特触发输入的逻辑芯片。