原创 是时候学习SystemVerilog了

是时候学习SystemVerilog了

<?xml:namespace prefix = st1 ns = "urn:schemas-microsoft-com:office:smarttags" />1/19/2006 Global Designer: IEEE standardizes SystemVerilog

May 25, 2006 SystemVerilog Gains A Foothold In Verification

2006-10-12 SystemVerilog已在验证领域立稳脚跟

01/08/2007 SystemVerilog adoption up, Cadence survey says

08/24/2007 Accellera Approves Functional Design Verification Standard

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Synopsys and VMM

Feb 16, 2004 Arm and Synopsys to Deliver Industry's First Reference Verification Methodology Based on SystemVerilog

Sep 21, 2005 Synopsys Announces Source-Code License for SystemVerilog Verification Library

Mar 20, 2006 Synopsys Delivers First Complete SystemVerilog Design and Verification Flow

Jul 18, 2006 Industry Momentum Builds for the ARM-Synopsys VMM for SystemVerilog

Jul 26, 2006 Synopsys Donates Library of Advanced SystemVerilog Assertion Checkers to Accellera Standards Organization

Mar 5, 2007 Synopsys Extends VMM Methodology for Higher Functional Verification Productivity

May 14, 2007 Leading Semiconductor Companies in China Adopt the VMM Verification Methodology

2007-05-15 Synopsys在华确立VMM验证方法标准

2007-5-15 《SystemVerilog验证方法学》中文版首发式

Jun 5, 2007 Synopsys Launches VMM Catalyst Program With More Than 50 Member Companies

Mentor Graphics and AVM

Advanced Verification Methodology (AVM) Cookbook for SystemVerilog and SystemC

March 30, 2005 Mentor Graphics Donation of SystemVerilog Assertion Version of Open Verification Library Accepted by Accellera

May 8, 2006 Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem

09 May 2006 Mentor Unveils Next Generation Verification Solution

2006年07月04日 开放式方法论和UCDB促进下一代功能验证

May 31, 2007 Denali and Mentor Team to Enable Verification IP for SystemVerilog Verification Environments

Cadence and uRM/UVM

THE UNIFIED VERIFICATION METHODOLOGY

Incisive Plan-to-closure Methodology

06/15/2004 Cadence promises full SystemVerilog support

10/24/2005 Cadence joins SystemVerilog party, offers new bundles

10/24/2005 DESIGN LANGUAGES: Verisity verification tools tuned for SystemVerilog

11/14/2005 Cadence segments Incisive verification platform

Cadence and Mentor Graphics and OVM

8/16/2007 Cadence and Mentor create free, open-source SystemVerilog methodology

August 16, 2007 Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology

August 16, 2007 Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology

20 Aug 2007 CADENCE与MENTOR GRAPHICS通过开放的SYSTEMVERILOG验证方法学实现协作

08/16/2007 Cadence, Mentor team on SystemVerilog verification

08/17/2007 Synopsys was not invited to join SystemVerilog OVM initiative

What others are saying

Faster verification is the goal at ST

VMM Users Group

VMM based env

Mentor on AVM

Strange Bedfellows - Cadence, Mentor, and the OVM

Synopsys/Intel and the OVM

SystemVerilog Methodologies – It’s Getting Wild

学习资料：

http://www.eda.org/sv/SystemVerilog_3.1a.pdf

Accellera Standard OVL V2

AVM Cookbook for SystemVerilog & SystemC 3.0

AMBA 3 Specification and Assertions