原创 多相抽取fir滤波器的fpga仿真实现
今天仿真了下多相抽取滤波器的仿真实现，其原理其实很简单就是根据抽取的原则，将fir滤波器的系统函数分解，称之为多相，所以又叫多相抽取滤波器。
一、原理如下图：
系统实现函数为：
二、参考一篇论文和田耕书仿真如下：
结合matlab参数进行测试,代码贴在最后面：
matlab输出结果：
modesim仿真结果如下：
两者结果还是相同的。。
现在把源代码贴在下面：
matlab代码：
close all;clc;clear all;
h = [0.48301 0.8365 0.2241 -0.1294];
NX = 9;
x_in = 0:NX-1;
x1 = filter(h,1,x_in);
M=2;
y1 = x1(1:M:NX);
y = fix(y1);
stem(y)
fpga代码：
part1：
module polyfilter(clk,clk2,reset,x_in,y_out);
parameter even = 0,odd =1;
input clk;
input clk2;
input reset;
input [7:0] x_in;
output [8:0] y_out;
reg [16:0] m0,m1,m2,m3,r0,r1,r2,r3;
reg [16:0] x33,x99,x107;
reg [16:0] y;
reg [7:0] x_odd,x_even,x_wait;
wire [16:0] x_odd_sxt,x_even_sxt;
reg state;
always @(posedge clk ) begin
if(!reset) begin
state <= odd;
x_even <= 0;
x_odd <= 0;
x_wait <= 0;
end
else begin
case(state)
even:begin
x_even <= x_in;
x_odd <= x_wait;
state <= odd;
end
odd: begin
x_wait <= x_in;
state <= even;
end
endcase
end
end
assign x_odd_sxt = {{9{x_odd[7]}},x_odd};
assign x_even_sxt = {{9{x_even[7]}},x_even};
always @(posedge clk) begin
if(!reset) begin
x33 =0;
x99 = 0;
x107 = 0;
m0 =0;
m1 = 0;
m2 =0;
m3 =0;
end
else begin
x33 = (x_odd_sxt << 5) + x_odd_sxt;
x99 = (x33 << 1) + x33;
x107 = x99 + (x_odd_sxt <<3);
m0 = (x_even_sxt << 7) - (x_even_sxt <<2);
m1 = x107 << 1;
m2 = (x_even_sxt << 6);
m3 = x33;
end
end
always @(posedge clk2) begin
if(!reset) begin
r0 <= 0 ;
r1 <= 0;
r2 <= 0;
r3 <= 0;
end
else begin
r0 <= r2 + m0;
r2 <= m2;
r1 <= -r3 + m1;
r3 <= m3;
y <= r0 + r1;
end
end
assign y_out = y[16:8];
endmodule
part2：
module polyfilter_tb();
reg clk;
reg clk2;
reg reset;
reg [7:0] x_in_d1;
wire [8:0] y_out;
reg [7:0] x_in[8:0];
polyfilter polyfilter_d1(
.clk(clk),
.clk2(clk2),
.reset(reset),
.x_in(x_in_d1),
.y_out(y_out));
initial begin
clk =0;
reset =0 ;
clk2 =1;
#20 reset = 1;
end
always #4 clk <= ~clk;
always @(posedge clk)
clk2 <= ~clk2;
reg [3:0] count;
//就只输入9个数和matlab一致
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
x_in_d1 <= 8'd0;
x_in[8] <= 8'd8;
x_in[7] <= 8'd7;
x_in[6] <= 8'd6;
x_in[5] <= 8'd5;
x_in[4] <= 8'd4;
x_in[3] <= 8'd3;
x_in[2] <= 8'd2;
x_in[1] <= 8'd1;
x_in[0] <= 8'd0;
count <= 4'd0;
end
else if(count == 4'd9)
begin
count <= count;
x_in_d1 <= 8'd0;
end
else
begin
count <= count + 1;
x_in_d1 <= x_in[count];
end
end
endmodule
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用户1069018 2015-9-28 16:47
自做自受 2014-1-17 22:56
用户377235 2014-1-6 09:11