原创 FPGA学习之时钟分频

FPGA学习之分频

在FPGA学习过程中会遇到许多不同的时钟信号，要实现这些所需的时钟一般要经过时钟的分频与倍频，本文所实现的是时钟的分频，其中最常见的是奇数分频与偶数分频。程序中通过输入要实现的分频数N便可实现对应时钟的奇偶数分频，以下两图分别是N=6与N=7时的Modelsim仿真波形：

N=6时

N=7时

Verilog程序如下：

module Divider(

               clk,

                               rst_n,

                               clk1,

                               clk2,

                               clk_out

                              );

input clk;

input rst_n;

output clk_out;

output clk1;

output clk2;

wire clk_out;

reg clk1;

reg clk2;

reg [2:0] k1;

reg [2:0] k2;

parameter N=7; //要现实的N分频

always @(posedge clk,negedge rst_n)

begin

  if(!rst_n)

    begin

            k1<=3'b0;

                   clk1<=1'b0;

          end

  else

            if(k1<(N-1))

                     begin

                       k1<=k1+3'b1;

                             if(k1<(N-1)/2)

                                clk1<=1'b0;

                       else if (k1>=(N-1)/2)

                clk1<=1'b1;        

                     end

                    else

                       begin

                         clk1<=1'b0; 

                         k1<=3'b0;

                end

end

always @(negedge clk,negedge rst_n)

begin

  if(!rst_n)

    begin

            k2<=3'b0;

                   clk2<=1'b0;

          end

  else

            if(k2<(N-1))

                     begin

                       k2<=k2+3'b1;

                             if(k2<(N-1)/2)

                                clk2<=1'b0;

                       else if (k2>=(N-1)/2)

                clk2<=1'b1;        

                     end

                    else

                       begin

                         clk2<=1'b0; 

                         k2<=3'b0;

                end

end  

assign clk_out=(N%2)? (clk1|clk2):clk1;

endmodule