原创 【博客大赛】数模转换----束手就擒吧

图2

程序代码如下：

module spi_da(

        clk,

        rst,

        data_par,

        spi_syn,

        spi_clk,

        spi_simo);

input clk;//16Mhz系统时钟；

input rst;//低电平有效的复位信号；

input [15:0] data_par;//待发送的16位并行数据；

 

output reg spi_syn;

//SPI接口的同步信号，低电平有效；

output reg spi_clk;

//SPI接口的串行时钟，下降沿将数据写入DA的内部移位寄存器；

output reg spi_simo;

//SPI接口的串行输入数据；

 

reg [3:0] p_count;//上电后一直自加的计数器；

reg [3:0] wait_count;//等待状态的计数器；

reg [6:0] conv_count;//转换状态的计数器；

reg [15:0] data_reg;//锁存的16位寄存器；

 

parameter IDLE =3'b001;

parameter CONV =3'b010;

parameter WAIT  =3'b100;

 

reg [2:0] cstate;

reg [2:0] nstate;

 

always @ (posedge clk or negedge rst)

    if(rst==0)

        p_count<=4'b0;

    else

        p_count<=p_count+1;

//上电后一直自加的计数器；

         

always @ (posedge clk or negedge rst)

    if(rst==0)

        wait_count<=4'b0;

    else if(cstate==WAIT || nstate==WAIT)

        wait_count<=wait_count+1;

    else

        wait_count<=4'b0;

//等待状态的计数器；

           

always @ (posedge clk or negedge rst)

    if(rst==0)

        conv_count<=7'b0;

    else if(cstate==CONV || nstate==CONV)

        conv_count<=conv_count+1;

    else

        conv_count<=7'b0;

//转换状态的计数器；

 

always @ (posedge clk or negedge rst)

    if(rst==1'b0)

        cstate<=IDLE;

    else

        cstate<=nstate;

//当前状态等于下一状态

       

always @ (cstate,p_count,conv_count,wait_count)

    begin

        nstate=IDLE;

        case(cstate)

            IDLE:

                begin

                    if(p_count==4'hE)

                        nstate=WAIT;

                    else

                        nstate=IDLE;

                end

            WAIT:

                begin

                    if(wait_count==4'hE)

                        nstate=CONV;

                    else

                        nstate=WAIT;

                end

            CONV:

                begin

                    if(conv_count==7'd32)

                        nstate=WAIT;

                    else

                        nstate=CONV;

                end        

            default:

                begin

                end

        endcase

    end

//产生下一状态

   

always @ (posedge clk or negedge rst)

    begin

        if(rst==1'b0)

            begin

                spi_syn<=1'b1;

                spi_simo<=1'b0;

                data_reg<=16'b0;

                spi_clk<=1'b1;

            end

        else

            begin

                case(nstate)

                    IDLE:

                        begin

                            spi_syn<=1'b1;

                            spi_simo<=1'b0;

                            data_reg<=16'b0;

                            spi_clk<=1'b1;

                        end

                    WAIT:

                        begin

                            spi_syn<=1'b1;

                            spi_simo<=1'b0;

                            spi_clk<=1'b1;

                            if(wait_count==4'h6)

                                begin

                                    data_reg<=data_par;

                                end

                            else

                                begin

                                    data_reg<=data_reg;

                                end

                        end

                    CONV:

                        begin

                            spi_syn<=1'b0;

                            spi_simo<=data_reg[15];

                            if(conv_count==7'd0)

                                begin

                                    spi_clk<=1'b1;

                                end

                            else

                                begin

                                    spi_clk<=!spi_clk;

                                end

                            if(conv_count[0]==1'b1)

                                begin

                                    data_reg<={data_reg[14:0],1'b0};

                                end

                            else

                                begin

                                    data_reg<=data_reg;

                                end

                        end                

                    default:

                        begin

                            spi_syn<=1'b1;

                            spi_simo<=1'b0;

                            data_reg<=data_reg;

                            spi_clk<=1'b1;

                        end

                endcase

                   

            end

    end

//输出SPI接口的3个信号：同步信号、串行时钟、串行数据。

 

endmodule

 

 

DA模块的仿真波形图见图3，波形图中发送的数据为55AA。