原创 VHDL电子时钟程序（续）

网友热心提供了VHDL 电子时钟设计程序代码，并指出我的程序存在的问题，在此感激不尽。下面是接着上篇博文的时钟设计程序。

VHDL电子钟程序（例化程序）library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity electronic_clock is

    Port ( clk50MHZ,kys,kym,Tin,rstin : in STD_LOGIC;

            oe,er : out std_logic_vector(2 downto 0);

                segments: out std_logic_vector(7 downto 0);

                     positions : out std_logic_vector(7 downto 0));

end electronic_clock;

architecture Behavioral of electronic_clock is

component frequncy_divider

Port ( clk : in STD_LOGIC;

       clk2HZ,clk100HZ,clk200HZ,clk1MHZ: out std_logic);

end component ;

component Sac

Port ( keys,clk_200HZ,clk_2HZ : in STD_LOGIC;

                  clks : out std_logic_vector(5 downto 0);

              selector : out std_logic_vector(3 downto 0));

end component ;

component buttoms

Port ( keym,clk200HZi : in STD_LOGIC;

                   kymj : out std_logic);

end component ;

component miseconds

Port ( clk_100HZ,rst1 : in STD_LOGIC;

                      A : out std_logic;

                  dat10 : out std_logic_vector(7 downto 0));

end component;

component seconds

Port ( rst2,selector1,ky_1j : in STD_LOGIC;

                  A10 : in std_logic;

                                B : out std_logic;

                        dat20 : out std_logic_vector(7 downto 0));

end component;

component minutes

Port ( rst3,selector2,ky_2j : in STD_LOGIC;

                  B10 : in std_logic;

                                C : out std_logic;

                        dat30 : out std_logic_vector(7 downto 0));

end component;

component hours

Port ( rst4,selector3,ky_3j : in STD_LOGIC;

                  C10 : in std_logic;

                        dat40 : out std_logic_vector(7 downto 0));

end component;

component scannor

Port ( clk_1MHZ,T : in std_logic;

           clks : in std_logic_vector(5 downto 0);

             D : in std_logic_vector(31 downto 0);   

             bt : out std_logic_vector(7 downto 0);                           

              led8s : out std_logic_vector(7 downto 0));

end component;

signal clk_2HZi,clk_100HZi,clk_200HZi,clk_1MHZi :std_logic;

signal a11,b11,c11 : std_logic;

signal kys_x : std_logic_vector(3 downto 0);

signal kym_j : std_logic;

signal clk_s :std_logic_vector(5 downto 0);

signal k : std_logic_vector(31 downto 0);

begin

u1 : frequncy_divider port map(clk=>clk50MHZ,clk2HZ=>clk_2HZi,clk100HZ=>clk_100HZi,clk200HZ=>clk_200HZi,clk1MHZ=>clk_1MHZi);

u2 : Sac               port map(keys=>kys,clk_200HZ=>clk_200HZi,clk_2HZ=>clk_2HZi,clks=>clk_s,selector=>kys_x);

u3 : buttoms            port map(keym=>kym,clk200HZi=>clk_200HZi,kymj=>kym_j);

u4 : miseconds          port map(clk_100HZ=>clk_100HZi,rst1=>rstin,A=>a11,dat10=>k(7 downto 0));

u5 : seconds            port map(rst2=>rstin,selector1=>kys_x(1),A10=>a11,ky_1j=>kym_j,B=>b11,dat20=>k(15 downto 8));

u6 : minutes           port map(rst3=>rstin,selector2=>kys_x(2),B10=>b11,ky_2j=>kym_j,C=>c11,dat30=>k(23 downto 16));

u7 : hours           port map(rst4=>rstin,selector3=>kys_x(3),C10=>c11,ky_3j=>kym_j,dat40=>k(31 downto 24));

u8 : scannor          port map(clk_1MHZ=>clk_1MHZi,T=>Tin,clks=>clk_s,D=>k,bt=> positions,led8s=>segments);

oe<="000" ;er<="011";

end Behavioral;

这个程序为电子 钟的主程序（例化程序），在所包括的器件中:

   hours为小时计数

   minutes为分钟计数

   seconds为秒计数。

   misecond为毫秒计数

scannor为数码管显示扫描

buttoms为手动加1调整按钮，防抖动。

frequncy_divider为分频器。

sac为选择控制程序，将数据（小时，分钟，秒）选中，选中后，数据会有闪烁效果，然后手动进行调整。

VHDL电子钟程序（按钮，选择控制，及引脚锁定）l
ibrary IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity buttoms is

    Port ( keym,clk200HZi : in STD_LOGIC;

               kymj : out std_logic);

end buttoms;

architecture Behavioral of buttoms is

signal q1,q2 : std_logic;

begin

process(keym,clk200HZi)

begin

if keym='1' then

q1<='0';q2<='0';

elsif clk200HZi'event and clk200HZi='1'

then q1<='1';q2<=q1;

end if;

end process ;

kymj<=q1 and q2;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Sac is

    Port ( keys,clk_200HZ,clk_2HZ : in STD_LOGIC;

               clks : out std_logic_vector(5 downto 0);

           selector : out std_logic_vector(3 downto 0));

end Sac;

architecture Behavioral of Sac is

signal cnt8 : STD_LOGIC_vector(1 downto 0):="00";

signal clks1 : std_logic_vector(5 downto 0):="111111";

signal q1,q2,q3 : std_logic;

begin

P1: process(clk_200HZ,keys)

begin

if keys='1' then

q1<='0';q2<='0';

elsif clk_200HZ'event and clk_200HZ='1'

then q1<='1';q2<=q1;

end if;

end process p1;

q3<=q1 and q2;

P2: process(clk_200HZ)

begin

if clk_200HZ'event and clk_200HZ='1' then

case cnt8 is

when "00" => selector <= "0000" ;clks<="111111";

when "01" => selector <= "1000" ;clks(5)<=clk_2HZ;clks(4)<=clk_2HZ;clks(3 downto 0)<="0000";

when "10" => selector <= "0100" ;clks(3)<=clk_2HZ;clks(2)<=clk_2HZ;clks(5 downto 4)<="00";clks(1 downto 0)<="00";

when "11" => selector <= "0010" ;clks(1)<=clk_2HZ;clks(0)<=clk_2HZ;clks(5 downto 2)<="0000";

when others => null ;

end case ;

end if ;

end process P2 ;

P3 : process(q3)

begin

if q3'event and q3 ='1' then cnt8 <= cnt8+1;

end if ;

end process P3;

end Behavioral;

net "clk50MHZ" loc = "A11" ;

net "rstin"   loc = "k22" ;

net "Tin"     loc = "k21" ;

net "kys"   loc = "j22" ;

net "kym"   loc = "j21" ;

net " segments(0)" loc = "y22" ;

net " segments(1)" loc = "w21" ;

net " segments(2)" loc = "w22" ;

net " segments(3)" loc = "v21" ;

net " segments(4)" loc = "v22" ;

net " segments(5)" loc = "u21" ;

net " segments(6)" loc = "t21" ;

net " segments(7)" loc = "t22" ;

net "positions(0)" loc = "y1" ;

net " positions(1)" loc = "w2" ;

net " positions(2)" loc = "w1" ;

net " positions(3)" loc = "v2" ;

net " positions(4)" loc = "v1" ;

net " positions(5)" loc = "u2" ;

net " positions(6)" loc = "T2" ;

net " positions(7)" loc = "T1" ;

net “oe(0)" loc = "y2" ;

net "oe(1)" loc = "y21" ;

net "oe(2)" loc = "l22" ;

net "er(0)" loc = "v3" ;

net "er(1)" loc = "v20" ;
net "er(2)" loc = "f17" ;