原创 VHDL电子时钟程序

最近收到网上朋友们来信咨询如何设计电子时钟，也有很多热心朋友把他设计的时钟或时钟程序发给我。因时间和水平有限不能一一回复和审查到底哪些是合格或是网络转载的。但是感觉可能对部分网友会有所用处，就把自己手头已有的一些时钟设计的相关资料放到网上，希望大家能多多包涵。我会不定时的把一些时钟设计资料上传到本博客，希望多多关注。

下面是电子时钟设计的部分VHDL程序代码。

VHDL电子钟程序（小时和分钟）

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity hours is

Port ( rst4,selector3,ky_3j : in STD_LOGIC;

                  C10 : in std_logic;

                        dat40 : out std_logic_vector(7 downto 0));

end hours;

architecture Behavioral of hours is

signal dat41,dat42 : std_logic_vector(7 downto 0):=(others =>'0');

begin

process(rst4,C10,ky_3j)

begin

case selector3 is

when '1' => dat42<=dat41; if ky_3j'event and ky_3j='1' then

if dat41(7 downto 4)="0010" and dat41(3 downto 0)="0011"

then dat41<="00000000";

elsif dat41(3 downto 0)<"1001" then dat41(3 downto 0)<=dat41(3 downto 0)+1;

else dat41(3 downto 0)<="0000";dat41(7 downto 4)<=dat41(7 downto 4)+1;

end if ;

end if ;

dat40<=dat41;

when '0' => dat41<=dat42; if(rst4 = '0') then dat42<=(others =>'0');

elsif C10'event and C10='1' then

if dat42(7 downto 4)="0010" and dat42(3 downto 0)="0011"

then dat42<="00000000";

elsif dat42(3 downto 0)<"1001" then dat42(3 downto 0)<=dat42(3 downto 0)+1;

else dat42(3 downto 0)<="0000";dat42(7 downto 4)<=dat42(7 downto 4)+1;

end if;

end if;

dat40<=dat42;

when others =>null;

end case;

end process;

end Behavioral;

VHDL电子钟程序（分频和秒计数）
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity miseconds is

    Port ( clk_100HZ,rst1 : in STD_LOGIC;

                          A : out std_logic;

                      dat10 : out std_logic_vector(7 downto 0));

end miseconds;

architecture Behavioral of miseconds is

signal dat1 : std_logic_vector(7 downto 0):=(others =>'0');

begin

process(clk_100HZ,rst1)

begin

if(rst1 = '0') then dat1<=(others =>'0');

elsif clk_100HZ'event and clk_100HZ='1' then

if dat1(7 downto 4)="1001" and dat1(3 downto 0)="1001"

then A<='1'; dat1(7 downto 0)<="00000000";

else A<='0';

if dat1(3 downto 0)<"1001" then dat1(3 downto 0)<=dat1(3 downto 0)+1;

else dat1(3 downto 0)<="0000";

if dat1(7 downto 4)<"1001" then dat1(7 downto 4)<=dat1(7 downto 4)+1;

else dat1(7 downto 4)<="0000";

end if;

end if;

end if;

end if;

end process;

dat10<=dat1;

end Behavioral;

VHDL电子钟程序（数码管显示扫描程序）
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity scannor is

Port ( clk_1MHZ,T : in std_logic;

           clks : in std_logic_vector(5 downto 0);

             D : in std_logic_vector(31 downto 0);

             positions : out std_logic_vector(7 downto 0);                           

             segments : out std_logic_vector(7 downto 0));

end scannor;

architecture Behavioral of scannor is

signal cnt8:STD_LOGIC_vector(2 downto 0);

signal sin :STD_LOGIC_vector(7 downto 0);

signal d1 :   STD_LOGIC_vector(3 downto 0);

signal bt1 : std_logic_vector(7 downto 0);

begin

P1: process(clk_1MHZ)

begin

if (clk_1MHZ'event and clk_1MHZ='1') then

case cnt8 is

when "000" => sin <= "00000001" ; d1 <= D(3 downto 0) ;   led8s(7) <= '0';

when "001" => sin <= "00000010" ; d1 <= D(7 downto 4) ;   led8s(7) <= '0';

when "010" => sin <= "00000100" ; d1 <= D(11 downto 8) ; led8s(7) <= '1';

when "011" => sin <= "00001000" ; d1 <= D(15 downto 12) ; led8s(7) <= '0';

when "100" => sin <= "00010000" ; d1 <= D(19 downto 16) ; led8s(7) <= '1';

when "101" => sin <= "00100000" ; d1 <= D(23 downto 20) ; led8s(7) <= '0';

when "110" => sin <= "01000000" ; d1 <= D(27 downto 24) ; led8s(7) <= '1';

when "111" => sin <= "10000000" ; d1 <= D(31 downto 28) ; led8s(7) <= '0';

when others => null ;

end case ;

end if ;

end process P1;

P2 : process(clk_1MHZ)

begin

if clk_1MHZ'event and clk_1MHZ ='1' then cnt8 <= cnt8+1;

end if ;

end process P2;

P3 : process(d1)

begin

case d1 is

when "0000" => led8s(6 downto 0) <= "0111111" ;

when "0001" => led8s(6 downto 0) <= "0000110" ;

when "0010" => led8s(6 downto 0) <= "1011011" ;

when "0011" => led8s(6 downto 0) <= "1001111" ;

when "0100" => led8s(6 downto 0) <= "1100110" ;

when "0101" => led8s(6 downto 0) <= "1101101" ;

when "0110" => led8s(6 downto 0) <= "1111101" ;

when "0111" => led8s(6 downto 0) <= "0000111" ;

when "1000" => led8s(6 downto 0) <= "1111111" ;

when "1001" => led8s(6 downto 0) <= "1101111" ;

when others => null ;

end case ;

end process P3;

bt1(0) <= sin(0) ;

bt1(1) <= sin(1) ;

bt1(2) <= sin(2) and clks(0) ;

bt1(3) <= sin(3) and clks(1) ;

bt1(4) <= sin(4) and clks(2) ;

bt1(5) <= sin(5) and clks(3) ;

bt1(6) <= sin(6) and clks(4) ;

bt1(7) <= sin(7) and clks(5) ;

bt(0)<=not(bt1(0)and T);

bt(1)<=not(bt1(1)and T);

bt(2)<=not(bt1(2)and T);

bt(3)<=not(bt1(3)and T);

bt(4)<=not(bt1(4)and T);

bt(5)<=not(bt1(5)and T);

bt(6)<=not(bt1(6)and T);

bt(7)<=not(bt1(7)and T);

end Behavioral;