原创时钟5分频

 2009-2-23 11:57  3304 6 6 分类: FPGA/CPLD

用Verilog设计一个5分频器。
       5分频，奇数分频都可以类似这么做,只需要改div1和div2的参数。div1为奇数分频除2的余数。采用上升延和下降延分别触发不同波形，最后叠加的方式产生奇数分频。
module divfreq(clk, clk1x, rst, clk1xpose, clk1xnege, coutpose, coutnege);
input clk;
input rst;
output clk1x;
output clk1xpose;
output clk1xnege;
output[2:0] coutpose;
output[2:0] coutnege;
reg clk1xpose;
reg clk1xnege;
reg[2:0] coutpose;
reg[2:0] coutnege;
parameter div1 = 2 , div2 = 4; // div1 ＝ 5 / 2, div2 = 5 - 1
assign clk1x = clk1xpose | clk1xnege;
always@(posedge clk or negedge rst)
begin
if(!rst)

    clk1xpose = 0;

else if(coutpose == div1)
    clk1xpose = ~clk1xpose;
else if(coutpose == div2)
    clk1xpose = ~clk1xpose;
else
    clk1xpose = clk1xpose;
end
always@(negedge clk or negedge rst)
begin
if(!rst)

    clk1xnege = 0;

else if(coutnege == div1)
   clk1xnege = ~clk1xnege;
else if(coutnege == div2)
   clk1xnege = ~clk1xnege;
else
   clk1xnege = clk1xnege;
end
always@(posedge clk or negedge rst)
begin
if(!rst)
   coutpose = 0;
else if(coutpose == div2)
   coutpose = 0;
else
   coutpose = coutpose + 1;
end
always@(negedge clk or negedge rst)
begin
if(!rst)
   coutnege = 0;
else if(coutnege == div2)
   coutnege = 0;
else
   coutnege = coutnege + 1;
end
endmodule

写原创有奖励！2024面包板原创奖励正在进行中