原创 Encounter_Command_Script: Clock Tree Synthesis

 2009-8-16 20:09  5017 3 3 分类: 工程师职场

#command for Soc Encounter5.2
#时钟树综合 timing constraint 修改内容
#set_propagated_clock versus set_clock_latency set_clock_transition
#set_dont_touch
#set_virtual_clock
#set_input_delay and set_output_delay
#set_clock_uncertanity
#before CTS
setup time=skew+jitter+margin hold time=skew+margin
#after CTS

setup time=jitter+margin hold time=smargin

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The goal of CTS is to synchrous all FF at same time, minimize skew and insertion delay. Clock is not propagated before CTS.

After CTS hold slack should improve. Clock tree begins at .sdc defined clock source and ends at stop pins of flop. There are two types of stop pins known as ignore pins and sync pins.
‘Don’t touch’ circuits and pins in front end (logic synthesis) are treated as ‘ignore’ circuits or pins at back end (physical synthesis).
‘Ignore’ pins are ignored for timing analysis. If clock is divided then separate skew analysis is necessary.

Global skew achieves zero skew between two synchronous pins without considering logic relationship.Local skew achieves zero skew between two synchronous pins while considering logic relationship.

If clock is skewed intentionally to improve setup slack then it is known as useful skew.

Rigidity is the term coined in Astro to indicate the relaxation of constraints. Higher the rigidity tighter is the constraints.

In Clock Tree Optimization (CTO) clock can be shielded so that noise is not coupled to other signals. But shielding increases area by 12 to 15%. Since the clock signal is global in nature the same metal layer used for power routing is used for clock also. CTO is achieved by buffer sizing, gate sizing, buffer relocation, level adjustment and HFN synthesis. We try to improve setup slack in pre-placement, in placement and post placement optimization before CTS stages while neglecting hold slack. In post placement optimization after CTS hold slack is improved. As a result of CTS lot of buffers are added. Generally for 100k gates around 650 buffers are added.

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High Performance Clock distribution
global clock distribution, local clock gated---Pulsed clock
www.ewubd.edu/~iraza/lect8EWU_Class_Clock_Design.pdf

https://ccnet.stanford.edu/cgi-bin/course.cgi?cc=ee371&action=handout_download&handout_id=ID124183722118645
C-element

https://ccnet.stanford.edu/cgi-bin/course.cgi?cc=ee371&action=handout_download&handout_id=ID124167754811522

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