/* Allow access to the bit fields or entire register */ union CANMD_REG { Uint32 all; struct CANMD_BITS bit; };
/* eCAN Transmit Request Set register (CANTRS) bit definitions */ struct CANTRS_BITS { // bit description Uint16 TRS0:1; // 0 TRS for Mailbox 0 Uint16 TRS1:1; // 1 TRS for Mailbox 1 Uint16 TRS2:1; // 2 TRS for Mailbox 2 Uint16 TRS3:1; // 3 TRS for Mailbox 3 Uint16 TRS4:1; // 4 TRS for Mailbox 4 Uint16 TRS5:1; // 5 TRS for Mailbox 5 Uint16 TRS6:1; // 6 TRS for Mailbox 6 Uint16 TRS7:1; // 7 TRS for Mailbox 7 Uint16 TRS8:1; // 8 TRS for Mailbox 8 Uint16 TRS9:1; // 9 TRS for Mailbox 9 Uint16 TRS10:1; // 10 TRS for Mailbox 10 Uint16 TRS11:1; // 11 TRS for Mailbox 11 Uint16 TRS12:1; // 12 TRS for Mailbox 12 Uint16 TRS13:1; // 13 TRS for Mailbox 13 Uint16 TRS14:1; // 14 TRS for Mailbox 14 Uint16 TRS15:1; // 15 TRS for Mailbox 15 Uint16 TRS16:1; // 16 TRS for Mailbox 16 Uint16 TRS17:1; // 17 TRS for Mailbox 17 Uint16 TRS18:1; // 18 TRS for Mailbox 18 Uint16 TRS19:1; // 19 TRS for Mailbox 19 Uint16 TRS20:1; // 20 TRS for Mailbox 20 Uint16 TRS21:1; // 21 TRS for Mailbox 21 Uint16 TRS22:1; // 22 TRS for Mailbox 22 Uint16 TRS23:1; // 23 TRS for Mailbox 23 Uint16 TRS24:1; // 24 TRS for Mailbox 24 Uint16 TRS25:1; // 25 TRS for Mailbox 25 Uint16 TRS26:1; // 26 TRS for Mailbox 26 Uint16 TRS27:1; // 27 TRS for Mailbox 27 Uint16 TRS28:1; // 28 TRS for Mailbox 28 Uint16 TRS29:1; // 29 TRS for Mailbox 29 Uint16 TRS30:1; // 30 TRS for Mailbox 30 Uint16 TRS31:1; // 31 TRS for Mailbox 31
};
/* Allow access to the bit fields or entire register */ union CANTRS_REG { Uint32 all; struct CANTRS_BITS bit; };
/* eCAN Transmit Request Reset register (CANTRR) bit definitions */ struct CANTRR_BITS { // bit description Uint16 TRR0:1; // 0 TRR for Mailbox 0 Uint16 TRR1:1; // 1 TRR for Mailbox 1 Uint16 TRR2:1; // 2 TRR for Mailbox 2 Uint16 TRR3:1; // 3 TRR for Mailbox 3 Uint16 TRR4:1; // 4 TRR for Mailbox 4 Uint16 TRR5:1; // 5 TRR for Mailbox 5 Uint16 TRR6:1; // 6 TRR for Mailbox 6 Uint16 TRR7:1; // 7 TRR for Mailbox 7 Uint16 TRR8:1; // 8 TRR for Mailbox 8 Uint16 TRR9:1; // 9 TRR for Mailbox 9 Uint16 TRR10:1; // 10 TRR for Mailbox 10 Uint16 TRR11:1; // 11 TRR for Mailbox 11 Uint16 TRR12:1; // 12 TRR for Mailbox 12 Uint16 TRR13:1; // 13 TRR for Mailbox 13 Uint16 TRR14:1; // 14 TRR for Mailbox 14 Uint16 TRR15:1; // 15 TRR for Mailbox 15 Uint16 TRR16:1; // 16 TRR for Mailbox 16 Uint16 TRR17:1; // 17 TRR for Mailbox 17 Uint16 TRR18:1; // 18 TRR for Mailbox 18 Uint16 TRR19:1; // 19 TRR for Mailbox 19 Uint16 TRR20:1; // 20 TRR for Mailbox 20 Uint16 TRR21:1; // 21 TRR for Mailbox 21 Uint16 TRR22:1; // 22 TRR for Mailbox 22 Uint16 TRR23:1; // 23 TRR for Mailbox 23 Uint16 TRR24:1; // 24 TRR for Mailbox 24 Uint16 TRR25:1; // 25 TRR for Mailbox 25 Uint16 TRR26:1; // 26 TRR for Mailbox 26 Uint16 TRR27:1; // 27 TRR for Mailbox 27 Uint16 TRR28:1; // 28 TRR for Mailbox 28 Uint16 TRR29:1; // 29 TRR for Mailbox 29 Uint16 TRR30:1; // 30 TRR for Mailbox 30 Uint16 TRR31:1; // 31 TRR for Mailbox 31
};
/* Allow access to the bit fields or entire register */ union CANTRR_REG { Uint32 all; struct CANTRR_BITS bit; };
/* eCAN Transmit Acknowledge register (CANTA) bit definitions */ struct CANTA_BITS { // bit description Uint16 TA0:1; // 0 TA for Mailbox 0 Uint16 TA1:1; // 1 TA for Mailbox 1 Uint16 TA2:1; // 2 TA for Mailbox 2 Uint16 TA3:1; // 3 TA for Mailbox 3 Uint16 TA4:1; // 4 TA for Mailbox 4 Uint16 TA5:1; // 5 TA for Mailbox 5 Uint16 TA6:1; // 6 TA for Mailbox 6 Uint16 TA7:1; // 7 TA for Mailbox 7 Uint16 TA8:1; // 8 TA for Mailbox 8 Uint16 TA9:1; // 9 TA for Mailbox 9 Uint16 TA10:1; // 10 TA for Mailbox 10 Uint16 TA11:1; // 11 TA for Mailbox 11 Uint16 TA12:1; // 12 TA for Mailbox 12 Uint16 TA13:1; // 13 TA for Mailbox 13 Uint16 TA14:1; // 14 TA for Mailbox 14 Uint16 TA15:1; // 15 TA for Mailbox 15 Uint16 TA16:1; // 16 TA for Mailbox 16 Uint16 TA17:1; // 17 TA for Mailbox 17 Uint16 TA18:1; // 18 TA for Mailbox 18 Uint16 TA19:1; // 19 TA for Mailbox 19 Uint16 TA20:1; // 20 TA for Mailbox 20 Uint16 TA21:1; // 21 TA for Mailbox 21 Uint16 TA22:1; // 22 TA for Mailbox 22 Uint16 TA23:1; // 23 TA for Mailbox 23 Uint16 TA24:1; // 24 TA for Mailbox 24 Uint16 TA25:1; // 25 TA for Mailbox 25 Uint16 TA26:1; // 26 TA for Mailbox 26 Uint16 TA27:1; // 27 TA for Mailbox 27 Uint16 TA28:1; // 28 TA for Mailbox 28 Uint16 TA29:1; // 29 TA for Mailbox 29 Uint16 TA30:1; // 30 TA for Mailbox 30 Uint16 TA31:1; // 31 TA for Mailbox 31
};
/* Allow access to the bit fields or entire register */ union CANTA_REG { Uint32 all; struct CANTA_BITS bit; };
/* eCAN Transmit Abort Acknowledge register (CANAA) bit definitions */ struct CANAA_BITS { // bit description Uint16 AA0:1; // 0 AA for Mailbox 0 Uint16 AA1:1; // 1 AA for Mailbox 1 Uint16 AA2:1; // 2 AA for Mailbox 2 Uint16 AA3:1; // 3 AA for Mailbox 3 Uint16 AA4:1; // 4 AA for Mailbox 4 Uint16 AA5:1; // 5 AA for Mailbox 5 Uint16 AA6:1; // 6 AA for Mailbox 6 Uint16 AA7:1; // 7 AA for Mailbox 7 Uint16 AA8:1; // 8 AA for Mailbox 8 Uint16 AA9:1; // 9 AA for Mailbox 9 Uint16 AA10:1; // 10 AA for Mailbox 10 Uint16 AA11:1; // 11 AA for Mailbox 11 Uint16 AA12:1; // 12 AA for Mailbox 12 Uint16 AA13:1; // 13 AA for Mailbox 13 Uint16 AA14:1; // 14 AA for Mailbox 14 Uint16 AA15:1; // 15 AA for Mailbox 15 Uint16 AA16:1; // 16 AA for Mailbox 16 Uint16 AA17:1; // 17 AA for Mailbox 17 Uint16 AA18:1; // 18 AA for Mailbox 18 Uint16 AA19:1; // 19 AA for Mailbox 19 Uint16 AA20:1; // 20 AA for Mailbox 20 Uint16 AA21:1; // 21 AA for Mailbox 21 Uint16 AA22:1; // 22 AA for Mailbox 22 Uint16 AA23:1; // 23 AA for Mailbox 23 Uint16 AA24:1; // 24 AA for Mailbox 24 Uint16 AA25:1; // 25 AA for Mailbox 25 Uint16 AA26:1; // 26 AA for Mailbox 26 Uint16 AA27:1; // 27 AA for Mailbox 27 Uint16 AA28:1; // 28 AA for Mailbox 28 Uint16 AA29:1; // 29 AA for Mailbox 29 Uint16 AA30:1; // 30 AA for Mailbox 30 Uint16 AA31:1; // 31 AA for Mailbox 31
};
/* Allow access to the bit fields or entire register */ union CANAA_REG { Uint32 all; struct CANAA_BITS bit; };
/* eCAN Received Message Pending register (CANRMP) bit definitions */ struct CANRMP_BITS { // bit description Uint16 RMP0:1; // 0 RMP for Mailbox 0 Uint16 RMP1:1; // 1 RMP for Mailbox 1 Uint16 RMP2:1; // 2 RMP for Mailbox 2 Uint16 RMP3:1; // 3 RMP for Mailbox 3 Uint16 RMP4:1; // 4 RMP for Mailbox 4 Uint16 RMP5:1; // 5 RMP for Mailbox 5 Uint16 RMP6:1; // 6 RMP for Mailbox 6 Uint16 RMP7:1; // 7 RMP for Mailbox 7 Uint16 RMP8:1; // 8 RMP for Mailbox 8 Uint16 RMP9:1; // 9 RMP for Mailbox 9 Uint16 RMP10:1; // 10 RMP for Mailbox 10 Uint16 RMP11:1; // 11 RMP for Mailbox 11 Uint16 RMP12:1; // 12 RMP for Mailbox 12 Uint16 RMP13:1; // 13 RMP for Mailbox 13 Uint16 RMP14:1; // 14 RMP for Mailbox 14 Uint16 RMP15:1; // 15 RMP for Mailbox 15 Uint16 RMP16:1; // 16 RMP for Mailbox 16 Uint16 RMP17:1; // 17 RMP for Mailbox 17 Uint16 RMP18:1; // 18 RMP for Mailbox 18 Uint16 RMP19:1; // 19 RMP for Mailbox 19 Uint16 RMP20:1; // 20 RMP for Mailbox 20 Uint16 RMP21:1; // 21 RMP for Mailbox 21 Uint16 RMP22:1; // 22 RMP for Mailbox 22 Uint16 RMP23:1; // 23 RMP for Mailbox 23 Uint16 RMP24:1; // 24 RMP for Mailbox 24 Uint16 RMP25:1; // 25 RMP for Mailbox 25 Uint16 RMP26:1; // 26 RMP for Mailbox 26 Uint16 RMP27:1; // 27 RMP for Mailbox 27 Uint16 RMP28:1; // 28 RMP for Mailbox 28 Uint16 RMP29:1; // 29 RMP for Mailbox 29 Uint16 RMP30:1; // 30 RMP for Mailbox 30 Uint16 RMP31:1; // 31 RMP for Mailbox 31
};
/* Allow access to the bit fields or entire register */ union CANRMP_REG { Uint32 all; struct CANRMP_BITS bit; };
/* eCAN Received Message Lost register (CANRML) bit definitions */ struct CANRML_BITS { // bit description Uint16 RML0:1; // 0 RML for Mailbox 0 Uint16 RML1:1; // 1 RML for Mailbox 1 Uint16 RML2:1; // 2 RML for Mailbox 2 Uint16 RML3:1; // 3 RML for Mailbox 3 Uint16 RML4:1; // 4 RML for Mailbox 4 Uint16 RML5:1; // 5 RML for Mailbox 5 Uint16 RML6:1; // 6 RML for Mailbox 6 Uint16 RML7:1; // 7 RML for Mailbox 7 Uint16 RML8:1; // 8 RML for Mailbox 8 Uint16 RML9:1; // 9 RML for Mailbox 9 Uint16 RML10:1; // 10 RML for Mailbox 10 Uint16 RML11:1; // 11 RML for Mailbox 11 Uint16 RML12:1; // 12 RML for Mailbox 12 Uint16 RML13:1; // 13 RML for Mailbox 13 Uint16 RML14:1; // 14 RML for Mailbox 14 Uint16 RML15:1; // 15 RML for Mailbox 15 Uint16 RML16:1; // 16 RML for Mailbox 16 Uint16 RML17:1; // 17 RML for Mailbox 17 Uint16 RML18:1; // 18 RML for Mailbox 18 Uint16 RML19:1; // 19 RML for Mailbox 19 Uint16 RML20:1; // 20 RML for Mailbox 20 Uint16 RML21:1; // 21 RML for Mailbox 21 Uint16 RML22:1; // 22 RML for Mailbox 22 Uint16 RML23:1; // 23 RML for Mailbox 23 Uint16 RML24:1; // 24 RML for Mailbox 24 Uint16 RML25:1; // 25 RML for Mailbox 25 Uint16 RML26:1; // 26 RML for Mailbox 26 Uint16 RML27:1; // 27 RML for Mailbox 27 Uint16 RML28:1; // 28 RML for Mailbox 28 Uint16 RML29:1; // 29 RML for Mailbox 29 Uint16 RML30:1; // 30 RML for Mailbox 30 Uint16 RML31:1; // 31 RML for Mailbox 31
};
/* Allow access to the bit fields or entire register */ union CANRML_REG { Uint32 all; struct CANRML_BITS bit; };
/* eCAN Remote Frame Pending register (CANRFP) bit definitions */ struct CANRFP_BITS { // bit description Uint16 RFP0:1; // 0 RFP for Mailbox 0 Uint16 RFP1:1; // 1 RFP for Mailbox 1 Uint16 RFP2:1; // 2 RFP for Mailbox 2 Uint16 RFP3:1; // 3 RFP for Mailbox 3 Uint16 RFP4:1; // 4 RFP for Mailbox 4 Uint16 RFP5:1; // 5 RFP for Mailbox 5 Uint16 RFP6:1; // 6 RFP for Mailbox 6 Uint16 RFP7:1; // 7 RFP for Mailbox 7 Uint16 RFP8:1; // 8 RFP for Mailbox 8 Uint16 RFP9:1; // 9 RFP for Mailbox 9 Uint16 RFP10:1; // 10 RFP for Mailbox 10 Uint16 RFP11:1; // 11 RFP for Mailbox 11 Uint16 RFP12:1; // 12 RFP for Mailbox 12 Uint16 RFP13:1; // 13 RFP for Mailbox 13 Uint16 RFP14:1; // 14 RFP for Mailbox 14 Uint16 RFP15:1; // 15 RFP for Mailbox 15 Uint16 RFP16:1; // 16 RFP for Mailbox 16 Uint16 RFP17:1; // 17 RFP for Mailbox 17 Uint16 RFP18:1; // 18 RFP for Mailbox 18 Uint16 RFP19:1; // 19 RFP for Mailbox 19 Uint16 RFP20:1; // 20 RFP for Mailbox 20 Uint16 RFP21:1; // 21 RFP for Mailbox 21 Uint16 RFP22:1; // 22 RFP for Mailbox 22 Uint16 RFP23:1; // 23 RFP for Mailbox 23 Uint16 RFP24:1; // 24 RFP for Mailbox 24 Uint16 RFP25:1; // 25 RFP for Mailbox 25 Uint16 RFP26:1; // 26 RFP for Mailbox 26 Uint16 RFP27:1; // 27 RFP for Mailbox 27 Uint16 RFP28:1; // 28 RFP for Mailbox 28 Uint16 RFP29:1; // 29 RFP for Mailbox 29 Uint16 RFP30:1; // 30 RFP for Mailbox 30 Uint16 RFP31:1; // 31 RFP for Mailbox 31
};
/* Allow access to the bit fields or entire register */ union CANRFP_REG { Uint32 all; struct CANRFP_BITS bit; };
/* eCAN Global Acceptance Mask register (CANGAM) bit definitions */ struct CANGAM_BITS { // bits description Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 Uint16 rsvd:2; // 30:29 reserved Uint16 AMI:1; // 31 AMI bit };
/* Allow access to the bit fields or entire register */ union CANGAM_REG { Uint32 all; struct CANGAM_BITS bit; };
/* eCAN Master Control register (CANMC) bit definitions */ struct CANMC_BITS { // bits description Uint16 MBNR:5; // 4:0 MBX # for CDR bit Uint16 SRES:1; // 5 Soft reset Uint16 STM:1; // 6 Self-test mode Uint16 ABO:1; // 7 Auto bus-on Uint16 CDR:1; // 8 Change data request Uint16 WUBA:1; // 9 Wake-up on bus activity Uint16 DBO:1; // 10 Data-byte order Uint16 PDR:1; // 11 Power-down mode request Uint16 CCR:1; // 12 Change configuration request Uint16 SCB:1; // 13 SCC compatibility bit Uint16 TCC:1; // 14 TSC MSB clear bit Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 Uint16 SUSP:1; // 16 SUSPEND free/soft bit Uint16 rsvd:15; // 31:17 reserved };
/* Allow access to the bit fields or entire register */ union CANMC_REG { Uint32 all; struct CANMC_BITS bit; };
/* Allow access to the bit fields or entire register */ union CANRIOC_REG { Uint32 all; struct CANRIOC_BITS bit; };
/* eCAN Time-out Control register (CANTOC) bit definitions */ struct CANTOC_BITS { // bit description Uint16 TOC0:1; // 0 TOC for Mailbox 0 Uint16 TOC1:1; // 1 TOC for Mailbox 1 Uint16 TOC2:1; // 2 TOC for Mailbox 2 Uint16 TOC3:1; // 3 TOC for Mailbox 3 Uint16 TOC4:1; // 4 TOC for Mailbox 4 Uint16 TOC5:1; // 5 TOC for Mailbox 5 Uint16 TOC6:1; // 6 TOC for Mailbox 6 Uint16 TOC7:1; // 7 TOC for Mailbox 7 Uint16 TOC8:1; // 8 TOC for Mailbox 8 Uint16 TOC9:1; // 9 TOC for Mailbox 9 Uint16 TOC10:1; // 10 TOC for Mailbox 10 Uint16 TOC11:1; // 11 TOC for Mailbox 11 Uint16 TOC12:1; // 12 TOC for Mailbox 12 Uint16 TOC13:1; // 13 TOC for Mailbox 13 Uint16 TOC14:1; // 14 TOC for Mailbox 14 Uint16 TOC15:1; // 15 TOC for Mailbox 15 Uint16 TOC16:1; // 16 TOC for Mailbox 16 Uint16 TOC17:1; // 17 TOC for Mailbox 17 Uint16 TOC18:1; // 18 TOC for Mailbox 18 Uint16 TOC19:1; // 19 TOC for Mailbox 19 Uint16 TOC20:1; // 20 TOC for Mailbox 20 Uint16 TOC21:1; // 21 TOC for Mailbox 21 Uint16 TOC22:1; // 22 TOC for Mailbox 22 Uint16 TOC23:1; // 23 TOC for Mailbox 23 Uint16 TOC24:1; // 24 TOC for Mailbox 24 Uint16 TOC25:1; // 25 TOC for Mailbox 25 Uint16 TOC26:1; // 26 TOC for Mailbox 26 Uint16 TOC27:1; // 27 TOC for Mailbox 27 Uint16 TOC28:1; // 28 TOC for Mailbox 28 Uint16 TOC29:1; // 29 TOC for Mailbox 29 Uint16 TOC30:1; // 30 TOC for Mailbox 30 Uint16 TOC31:1; // 31 TOC for Mailbox 31
};
/* Allow access to the bit fields or entire register */ union CANTOC_REG { Uint32 all; struct CANTOC_BITS bit; };
/* eCAN Time-out Status register (CANTOS) bit definitions */ struct CANTOS_BITS { // bit description Uint16 TOS0:1; // 0 TOS for Mailbox 0 Uint16 TOS1:1; // 1 TOS for Mailbox 1 Uint16 TOS2:1; // 2 TOS for Mailbox 2 Uint16 TOS3:1; // 3 TOS for Mailbox 3 Uint16 TOS4:1; // 4 TOS for Mailbox 4 Uint16 TOS5:1; // 5 TOS for Mailbox 5 Uint16 TOS6:1; // 6 TOS for Mailbox 6 Uint16 TOS7:1; // 7 TOS for Mailbox 7 Uint16 TOS8:1; // 8 TOS for Mailbox 8 Uint16 TOS9:1; // 9 TOS for Mailbox 9 Uint16 TOS10:1; // 10 TOS for Mailbox 10 Uint16 TOS11:1; // 11 TOS for Mailbox 11 Uint16 TOS12:1; // 12 TOS for Mailbox 12 Uint16 TOS13:1; // 13 TOS for Mailbox 13 Uint16 TOS14:1; // 14 TOS for Mailbox 14 Uint16 TOS15:1; // 15 TOS for Mailbox 15 Uint16 TOS16:1; // 16 TOS for Mailbox 16 Uint16 TOS17:1; // 17 TOS for Mailbox 17 Uint16 TOS18:1; // 18 TOS for Mailbox 18 Uint16 TOS19:1; // 19 TOS for Mailbox 19 Uint16 TOS20:1; // 20 TOS for Mailbox 20 Uint16 TOS21:1; // 21 TOS for Mailbox 21 Uint16 TOS22:1; // 22 TOS for Mailbox 22 Uint16 TOS23:1; // 23 TOS for Mailbox 23 Uint16 TOS24:1; // 24 TOS for Mailbox 24 Uint16 TOS25:1; // 25 TOS for Mailbox 25 Uint16 TOS26:1; // 26 TOS for Mailbox 26 Uint16 TOS27:1; // 27 TOS for Mailbox 27 Uint16 TOS28:1; // 28 TOS for Mailbox 28 Uint16 TOS29:1; // 29 TOS for Mailbox 29 Uint16 TOS30:1; // 30 TOS for Mailbox 30 Uint16 TOS31:1; // 31 TOS for Mailbox 31
};
/* Allow access to the bit fields or entire register */ union CANTOS_REG { Uint32 all; struct CANTOS_BITS bit; };
/**************************************/ /* eCAN Control & Status register file */ /**************************************/
struct ECAN_REGS { union CANME_REG CANME; // Mailbox Enable union CANMD_REG CANMD; // Mailbox Direction union CANTRS_REG CANTRS; // Transmit Request Set union CANTRR_REG CANTRR; // Transmit Request Reset union CANTA_REG CANTA; // Transmit Acknowledge union CANAA_REG CANAA; // Abort Acknowledge union CANRMP_REG CANRMP; // Received Message Pending union CANRML_REG CANRML; // Received Message Lost union CANRFP_REG CANRFP; // Remote Frame Pending union CANGAM_REG CANGAM; // Global Acceptance Mask union CANMC_REG CANMC; // Master Control union CANBTC_REG CANBTC; // Bit Timing union CANES_REG CANES; // Error Status union CANTEC_REG CANTEC; // Transmit Error Counter union CANREC_REG CANREC; // Receive Error Counter union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 union CANGIM_REG CANGIM; // Global Interrupt Mask 0 union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 union CANMIM_REG CANMIM; // Mailbox Interrupt Mask union CANMIL_REG CANMIL; // Mailbox Interrupt Level union CANOPC_REG CANOPC; // Overwrite Protection Control union CANTIOC_REG CANTIOC; // TX I/O Control union CANRIOC_REG CANRIOC; // RX I/O Control Uint32 CANTSC; // Time-stamp counter union CANTOC_REG CANTOC; // Time-out Control union CANTOS_REG CANTOS; // Time-out Status
/* Allow access to the bit fields or entire register */ union CANLAM_REG { Uint32 all; struct CANLAM_BITS bit; };
/**************************************/ /* eCAN Local Acceptance Masks */ /**************************************/
/* eCAN LAM File */ struct LAM_REGS { union CANLAM_REG LAM0; union CANLAM_REG LAM1; union CANLAM_REG LAM2; union CANLAM_REG LAM3; union CANLAM_REG LAM4; union CANLAM_REG LAM5; union CANLAM_REG LAM6; union CANLAM_REG LAM7; union CANLAM_REG LAM8; union CANLAM_REG LAM9; union CANLAM_REG LAM10; union CANLAM_REG LAM11; union CANLAM_REG LAM12; union CANLAM_REG LAM13; union CANLAM_REG LAM14; union CANLAM_REG LAM15; union CANLAM_REG LAM16; union CANLAM_REG LAM17; union CANLAM_REG LAM18; union CANLAM_REG LAM19; union CANLAM_REG LAM20; union CANLAM_REG LAM21; union CANLAM_REG LAM22; union CANLAM_REG LAM23; union CANLAM_REG LAM24; union CANLAM_REG LAM25; union CANLAM_REG LAM26; union CANLAM_REG LAM27; union CANLAM_REG LAM28; union CANLAM_REG LAM29; union CANLAM_REG LAM30; union CANLAM_REG LAM31; };
//=========================================================================== // No more. //===========================================================================
2、初始化文件
// // TMDX ALPHA RELEASE // Intended for product evaluation purposes // //########################################################################### // // FILE: DSP28_ECan.c // // TITLE: DSP28 Enhanced CAN Initialization & Support Functions. // //########################################################################### #include "DSP28_Device.h" // InitECan: This function initializes to a known state. //--------------------------------------------------------------------------- void InitECan(void) { struct ECAN_REGS ECanaShadow; /////////////////////////////////////////////////////////////////// ////**** Steps to Configure eCAN ****//// /////////////////////////////////////////////////////////////////// EALLOW; /*1, Configure eCAN RX and TX pins for eCAN transmissions using eCAN regs*/ ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; ECanaShadow.CANTIOC.bit.TXFUNC = 1; ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; ECanaShadow.CANRIOC.bit.RXFUNC = 1; ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; /*2, Configure eCAN for HECC mode (reqd to access mailboxes 16 thru 31) */ // HECC mode also enables time stamping feature ECanaRegs.CANMC.bit.SCB = 1; EDIS; /*3, Initialize all bits of ’Master Control Field’ to zero */ // Some bits of MCF register come up in an unknown state. For proper operation, // all bits (including reserved bits) of MCF must be initialized to zero ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000; // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again // as a matter of precaution. /*4, Clear all TAn bits */ ECanaRegs.CANTA.all = 0xFFFFFFFF; /*5, Clear all RMPn bits */ ECanaRegs.CANRMP.all = 0xFFFFFFFF; /*6, Clear all interrupt flag bits */ ECanaRegs.CANGIF0.all = 0xFFFFFFFF; ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
ECanaLAMRegs.LAM6.all=0x7FFFFFFF; /*7, Configure bit timing parameters */ EALLOW; ECanaRegs.CANMC.bit.CCR = 1 ; // Set CCR = 1 EDIS; while(ECanaRegs.CANES.bit.CCE != 1 ) {} // Wait for CCE bit to be set..
EALLOW; /*(BRPREG+1)=75 feeds a 2MHz CAN clock,100Kps bode-rate*/ ECanaRegs.CANBTC.bit.BRPREG = 74; ECanaRegs.CANBTC.bit.TSEG2REG = 2; ECanaRegs.CANBTC.bit.TSEG1REG = 15; ECanaRegs.CANMC.bit.CCR = 0 ; // Set CCR = 0 EDIS;
while(ECanaRegs.CANES.bit.CCE == !0 ) {} // Wait for CCE bit to be cleared.. /*8, Disable all Mailboxes */ ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs /////////////////////////////////////////////////////////////////////////////// //////**** Configuring Mailbox 5 for TX,Mailbox 6 for RX****//// /////////////////////////////////////////////////////////////////////////////// /*1, Write to the MSGID field */ ECanaMboxes.MBOX5.MSGID.all = 0x5FFFFFFF; // std Identifier ECanaMboxes.MBOX6.MSGID.all = 0x5FFFFFFF; // std Identifier
/* Write to DLC field in Master Control reg */ ECanaMboxes.MBOX5.MSGCTRL.all =0x8; ECanaMboxes.MBOX6.MSGCTRL.all =0x8; /* Write to the mailbox RAM field */ ECanaMboxes.MBOX5.MDL.all = 0xAAAAAAAA; ECanaMboxes.MBOX5.MDH.all = 0xAAAAAAAA; //* waiting for transmitting *// EALLOW; ECanaShadow.CANMC.all=ECanaRegs.CANMC.all; ECanaShadow.CANMC.bit.DBO=1; ECanaShadow.CANMC.bit.ABO=1; ECanaRegs.CANMC.all=ECanaShadow.CANMC.all; EDIS; /* Configure Mailbox under test as a Transmit mailbox */ ECanaShadow.CANMD.all = ECanaRegs.CANMD.all; ECanaShadow.CANMD.bit.MD5 = 0; ECanaShadow.CANMD.bit.MD6 = 1; ECanaRegs.CANMD.all = ECanaShadow.CANMD.all; /* Enable Mailbox under test */ ECanaShadow.CANME.all = ECanaRegs.CANME.all; ECanaShadow.CANME.bit.ME5 = 1; ECanaShadow.CANME.bit.ME6 = 1; ECanaRegs.CANME.all = ECanaShadow.CANME.all; /////////////////////////////////////////////////////////////////////////////// ////****End of Configuring Mailbox 5 for Transmit ****//// /////////////////////////////////////////////////////////////////////////////// } //=========================================================================== // No more. //===========================================================================
////**** Transmitting a Message by eCAN ****//// ///***1): clear CANTA flag ***/// ECanaRegs.CANME.all=0; EALLOW; ECanaShadow.CANMC.all=ECanaRegs.CANMC.all; ECanaShadow.CANMC.all=0x0105; ECanaRegs.CANMC.all=ECanaShadow.CANMC.all; EDIS; ///***2): Write the message data into the mailbox data field***/// ECanaMboxes.MBOX5.MDL.byte.BYTE1=0x55;//--BYTE1(31:24)
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