原创 简单5分频

module f_div(clk,rst_n,clk_out,clk_p,clk_n,count_r);
   
input clk;
input rst_n;
output clk_out;
output clk_p;
output clk_n;
output[3:0] count_r;

wire clk_out;
wire clk_p;
wire clk_n;

reg[3:0] count_r_p;
reg[3:0] count_r_n;
 
assign clk_p=(count_r_p<3);
assign clk_n=(count_r_n<3);
assign clk_out=(clk_p&clk_n);
assign count_r=count_r_p;

always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
       count_r_p<=0;    
    else
    begin
       if(count_r_p<4)
          count_r_p<=count_r_p+1'd1;
       else
          count_r_p<=0;
    end
end

always@(negedge clk)
begin
    if(!rst_n)
       count_r_n<=0;
    else
    begin
    if(count_r_n<4)
       count_r_n<=count_r_n+1'd1;
    else
       count_r_n<=0;
    end
end  
endmodule