原创 Quarts中的TimingAnalyzer给出的警告怎么分析处理？

综合人民邮电出版社出版的<?xml:namespace prefix = st1 ns = "urn:schemas-microsoft-com:office:smarttags" />刘韬老师提供的uart串行通讯模块FPGA实现程序时，Quarts提示的警告：

Warning: Found pins functioning as undefined clocks and/or memory enables<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

       Info: Assuming node "clk" is an undefined clock

Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

       Info: Detected ripple clock "baudrate_generator:U_BG|indicator" as buffer

       Info: Detected ripple clock "baudrate_generator:U_BG|bg_out" as buffer

       Info: Detected ripple clock "uart_core:U_Core|sel_clk" as buffer

       Info: Detected gated clock "switch:U_SRClkSwitch|dout~16" as buffer

       Info: Detected gated clock "switch:U_CounterClkSwitch|dout~4" as buffer

Info: Clock "clk" has Internal fmax of 84.75 MHz between source register "counter:U_Counter|overflow" and destination register "uart_core:U_Core|si_count[1]" (period= 11.8 ns)

       Info: + Longest register to register delay is 5.800 ns

              Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E41; Fanout = 14; REG Node = 'counter:U_Counter|overflow'

              Info: 2: + IC(2.400 ns) + CELL(0.600 ns) = 3.000 ns; Loc. = LC1_E20; Fanout = 4; COMB Node = 'uart_core:U_Core|Selector12~204'

              Info: 3: + IC(0.400 ns) + CELL(0.500 ns) = 3.900 ns; Loc. = LC8_E20; Fanout = 5; COMB Node = 'uart_core:U_Core|Selector12~205'

              Info: 4: + IC(0.800 ns) + CELL(0.600 ns) = 5.300 ns; Loc. = LC6_E18; Fanout = 1; COMB Node = 'uart_core:U_Core|Selector14~156'

              Info: 5: + IC(0.400 ns) + CELL(0.100 ns) = 5.800 ns; Loc. = LC8_E18; Fanout = 6; REG Node = 'uart_core:U_Core|si_count[1]'

              Info: Total cell delay = 1.800 ns ( 31.03 % )

              Info: Total interconnect delay = 4.000 ns ( 68.97 % )

       Info: - Smallest clock skew is -5.000 ns

              Info: + Shortest clock path from clock "clk" to destination register is 1.100 ns

                     Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 49; CLK Node = 'clk'

                     Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC8_E18; Fanout = 6; REG Node = 'uart_core:U_Core|si_count[1]'

                     Info: Total cell delay = 0.300 ns ( 27.27 % )

                     Info: Total interconnect delay = 0.800 ns ( 72.73 % )

              Info: - Longest clock path from clock "clk" to source register is 6.100 ns

                     Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 49; CLK Node = 'clk'

                     Info: 2: + IC(0.800 ns) + CELL(0.600 ns) = 1.700 ns; Loc. = LC7_E42; Fanout = 2; REG Node = 'baudrate_generator:U_BG|indicator'

                     Info: 3: + IC(1.900 ns) + CELL(0.500 ns) = 4.100 ns; Loc. = LC2_E22; Fanout = 33; COMB Node = 'switch:U_CounterClkSwitch|dout~4'

                     Info: 4: + IC(2.000 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC1_E41; Fanout = 14; REG Node = 'counter:U_Counter|overflow'

                     Info: Total cell delay = 1.400 ns ( 22.95 % )

                     Info: Total interconnect delay = 4.700 ns ( 77.05 % )

       Info: + Micro clock to output delay of source is 0.600 ns

       Info: + Micro setup delay of destination is 0.400 ns

Warning: Circuit may not operate. Detected 57 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.

请帮忙分析下。谢谢 ！

附图：警告界面截图。