原创 Tri-state (InOut and Output) Signals（EDK中的inout信号)

EDK中有时候要用到inout信号（比如和SRAM连接的DATA线），声明方法如下所述

Tri-state
(InOut and Output) Signals

A system
on a programmable chip design methodology follows these general rules of

thumb:

1. Submodule port driver directions (modes) should be either IN or OUT

2. Top level module/entity is allowed to have
ports of mode INOUT

The
drive direction (mode) of a port impacts the partitioning of a design. The mode
of a port
must propagate through all levels of hierarchy, with the result that if the
top-level requests
an inout port, then a low-level module must provide an inout port for connectivity.
Alternatively, at the top-level hierarchy, the user must describe the inout drive
direction to connect the lower-level, unidirectional ports of the submodule to
the toplevel bi-directional
inout port.

This
methodology fits well into an FGPA architecture since tri-state buffers are
only available
as an IOBUF primitive
in the IOB cell. A reduced implementation is a tri-output, which
Platgen maps to the OBUFT primitive.
Tri-states in the CLB do not exist; the synthesis tool translates the
tri-state logic to MUXes.

 An
abstract inout port on the MPD is defined for connectivity purposes. The
abstract port allows
a user to connect the top-level inout port to the lower-level abstract inout
port without
changing the partition or interface of the submodule in hardware.

At the
MHS/MPD level, there is an abstract inout port in the MPD file that allows a connection
through the IOBUF to the top-level inout port declaration in the MHS file. This
corresponds to the usage of defining an inout port at the top level and
preserving unidirectional ports at the lower level.

Note:
The tri-state
enable is active-low. This allows a direct connection to the OBUFT or the IOBUF without an inversion of the tri-state enable
port.

The IPIO port in Figure 3-0 is described as an abstract port of drive direction inout. This port is not listed on the port interface of the hardware module or
entity, as demonstrated in the following HDL code
examples.

In the MPD file, an abstract inout port is identified by the inout
direction mode and THREE_STATE=TRUE without defined TRI_I, TRI_O, and TRI_T
keywords. In this case, the abstract inout port name must share a common basename across the basename_I, basename_O, and
basename_T ports on the port interface
of the hardware module or entity. In Figure 3-0, the basename is IPIO. Platgen expands the inout port in the MPD file to _I, _O, and _T
ports in the port interface declaration of the HDL
file. This method does not allow the individual ports
that construct the abstract port to be listed in the MPD.

In the MPD file, an abstract inout port is identified by the inout
or output (tri-output) direction mode and THREE_STATE=TRUE with defined TRI_I, TRI_O, and TRI_T
keywords. In this case, the abstract
inout port name allows free connection to the individual ports that construct the abstract port. The abstract inout port or output
(tri-output) is freely named. This method does allow the
individual ports that construct the abstract port to be listed in the MPD.

Tri-state
(InOut) With Single-Bit Enable

MPD Example

BEGIN tri_state_single

OPTION IPTYPE=IP

PARAMETER C_WIDTH=9, DT=integer

PORT IPIO = “”, DIR=INOUT, VEC=[0:C_WIDTH-1],
ENABLE=SINGLE,

THREE_STATE=TRUE

END

Tri-state
(InOut) With Multi-Bit Enable

MPD Example

BEGIN tri_state_multi

OPTION IPTYPE=IP

PARAMETER C_WIDTH = 9, DT=integer

PORT IPIO = “”, DIR=INOUT, VEC=[0:C_WIDTH-1],
ENABLE=MULTI,

THREE_STATE=TRUE

END

Tri-state
(In/Out) With Single-Bit Enable With Freely Named Ports

MPD Example

BEGIN tri_state_single

OPTION IPTYPE=IP

PARAMETER C_WIDTH=9, DT=integer

PORT IPIO=“”,
DIR=IO,VEC=[0:C_WIDTH-1],THREE_STATE=TRUE, TRI_I=ITRI,

TRI_O=OTRI, TRI_T=TTRI

PORT ITRI=””, DIR=I, VEC=[0:C_WIDTH-1]

PORT OTRI=””, DIR=O, VEC=[0:C_WIDTH-1]

PORT TTRI=””, DIR=I

END

Tri-state
(InOut) With Multi-Bit Enable With Freely Named Ports

MPD Example

BEGIN tri_state_single

OPTION IPTYPE=IP

PARAMETER C_W=9, DT=integer

PORT IPIO=“”, DIR=IO, VEC=[0:C_WIDTH-1],
ENABLE=MULTI, TRI_I=ITRI,

TRI_O=OTRI, TRI_T=TTRI

PORT ITRI=””, DIR=I, VEC=[0:C_WIDTH-1]

PORT OTRI=””, DIR=O, VEC=[0:C_WIDTH-1]

PORT TTRI=””, DIR=I, VEC=[0:C_WIDTH-1]

END