Error: M4K memory block WYSIWYG primitive "RAM1:inst2|altsyncram:altsyncram_component|altsyncram_bqc1:auto_generated|altsyncram_4oe2:altsyncram1|ram_block3a0" utilizes the dual-port dual-clock mode. However, this mode is not supported in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature
用户377235 2014-12-15 18:42