原创 基于FPGA的数字摄像和显示（一）

想啊想，最后想到一个摄像头与显示系统，值得一做，那就动身吧…

看看都几点了，明天还要上班了，所以博文就简单点为好，附上自己的建模式SRAM的调试代码。

/* ************************************************************************************************
// Engineer     :   xymbmcu@163.com
// Target Device:   Altera Cyclone EP2C8Q208C8
// Clock   :   50Mhz
// Create Date :   2013-03-05 02:17
// Amend Date  :   
// Module Name :   SRAM_FunctionModule
// Project Name :   SRAM(IS61LV25616)
// Tool versions:   Quartus II 12.1
// Description :   写过程：isInOutSig_r = 1 --> WrData --> SRAM_Data(也即到了SRAM中)
       读过程：isInOutSig_r = 0 --> SRAM_Data --> RdData(也即到了上层阶级)
// Revision :   NO
// Additional Comments: 好好学学，这或许是你真正走进FPGA大门的金钥匙^_^
************************************************************************************************ */
module SRAM_FunctionModule(
         input Clk_50m,
         input Rst_n,
         
         input [1:0] FunStartSig, // [1] - write [0] read
         output RdWrDoneSig,   // read&&write complete!
         input [17:0] inSRAM_Addr, // 来自控制模块
         input [15:0] WrData,
         output [15:0] RdData,
         
         output [17:0] SRAM_Addr,
         output [4:0] SRAM_CMD,  // WE_n CE_n OE_n LB_n UB_n\
         inout [15:0] SRAM_Data
         );
// 定义命令常量
/* ------------------------------------------------------------------------- */
parameter SRAM_WrL8_CMD = 5'b00001, SRAM_WrU8_CMD = 5'b00010, SRAM_WrLU_CMD = 5'b00000,
    SRAM_RdL8_CMD = 5'b10001, SRAM_RdU8_CMD = 5'b10010, SRAM_RdLU_CMD = 5'b10000;
/* ------------------------------------------------------------------------- */

/* ========================================================================= */
reg [2:0] i_Step;

reg isInOutSig_r;
reg [4:0] SRAM_CMD_r;
reg [17:0] SRAM_Addr_r;
reg RdWrDoneSig_r;
reg [15:0] RdData_r;

always @ (posedge Clk_50m or negedge Rst_n)
 if(!Rst_n) begin
  isInOutSig_r <= 1'b1; // 默认为输出
  i_Step <= 3'd0;
  SRAM_Addr_r <= 18'd0;
  RdData_r <= 16'd0;
 end
 else if(FunStartSig[1])
  case (i_Step)
   // 设置为写（FPGA --> SRAM）
   0: begin isInOutSig_r <= 1'b1; i_Step <= i_Step + 1'b1; end
   // 写命令&&地址
   1: begin
    SRAM_CMD_r <= SRAM_WrLU_CMD;
    SRAM_Addr_r <= inSRAM_Addr;
    i_Step <= i_Step + 1'b1;
   end
   // 产生完成信号
   2: begin RdWrDoneSig_r <= 1'b1; i_Step <= i_Step + 1'b1; end
   
   3: begin RdWrDoneSig_r <= 1'b0; i_Step <= 3'd0; end
  endcase
  
 else if(FunStartSig[0])
  case (i_Step)
   // 设置为读（SRAM --> FPGA）
   0: begin isInOutSig_r <= 1'b0; i_Step <= i_Step + 1'b1; end
   // 写命令&&地址
   1: begin
    SRAM_CMD_r <= SRAM_RdLU_CMD;
    SRAM_Addr_r <= inSRAM_Addr;
    i_Step <= i_Step + 1'b1;    
   end
   2: begin RdData_r = SRAM_Data; i_Step <= i_Step + 1'b1; end
   // 产生完成信号
   3: begin RdWrDoneSig_r <= 1'b1; i_Step <= i_Step + 1'b1; end
   
   4: begin RdWrDoneSig_r <= 1'b0; i_Step <= 3'd0; end
  endcase
/* ========================================================================= */
assign SRAM_Data = isInOutSig_r ? WrData : 16'hzzzz;
assign RdWrDoneSig = RdWrDoneSig_r;
assign RdData = RdData_r;
assign SRAM_Addr = SRAM_Addr_r;
assign SRAM_CMD = SRAM_CMD_r;
/* ========================================================================= */
endmodule

这是调试代码：

module sram_test(
      input Clk_50m,
      input Rst_n,
      
      output [17:0] SRAM_Addr,
      output [4:0] SRAM_CMD,  // WE_n CE_n OE_n LB_n UB_n\
      inout [15:0] SRAM_Data,
      
      output PinTx
      );

parameter T1s = 26'd50000000; 
reg [25:0] m_Count;     
      
wire [1:0] FunStartSig_w;
wire RdWrDoneSig_w;
wire [17:0] inSRAM_Addr_w; 
wire [15:0] WrData_w;  
wire [15:0] RdData_w;   
SRAM_FunctionModule U1(
        .Clk_50m(Clk_50m),
        .Rst_n(Rst_n),
        
        .FunStartSig(FunStartSig_w), // Top to U1     [1] - write [0] read
        .RdWrDoneSig(RdWrDoneSig_w), // from U1    read&&write complete!
        .inSRAM_Addr(inSRAM_Addr_w), // Top to U1
        .WrData(WrData_w),    // Top to U1
        .RdData(RdData_w),
        // to pin
        .SRAM_Addr(SRAM_Addr),
        .SRAM_CMD(SRAM_CMD),  // WE_n CE_n OE_n LB_n UB_n\
        .SRAM_Data(SRAM_Data)
        ); 
  
wire TxEnSig_w; 
wire [7:0] TxData_w; 
wire TxDoneSig_w;
UART_TX U2(
    .Clk_50m(Clk_50m),
    .Rst_n(Rst_n),
    .TxEnSig(TxEnSig_w),
    .TxData(TxData_w),

    .PinTx(PinTx),    
    .TxDoneSig(TxDoneSig_w)
    );      
      
reg [3:0] j_Count;
reg [1:0] FunStartSig_r;
reg [17:0] inSRAM_Addr_r; 
reg [15:0] WrData_r;

reg [15:0] RdData_r;

reg TxEnSig_r;
reg [7:0] TxData_r;
always @ (posedge Clk_50m or negedge Rst_n)
 if(!Rst_n) begin
  j_Count <= 4'd0;
  FunStartSig_r <= 2'b00;
  inSRAM_Addr_r <= 18'd0;
  WrData_r <= 16'd0;
  RdData_r <= 16'd0;
  TxEnSig_r <= 1'b0;
  TxData_r <= 8'd0;
  m_Count <= 26'd0;
 end
 else case(j_Count)
  0: begin FunStartSig_r <= 2'd3; j_Count <= j_Count + 1'b1; end
  
  1: if(TxDoneSig_w) begin TxEnSig_r <= 1'b0; j_Count <= j_Count + 1'b1; end
   else begin TxEnSig_r <= 1'b1; TxData_r <= RdData_r[15:8]; end
  
  2: if(RdWrDoneSig_w) begin FunStartSig_r <= 2'b00; j_Count <= j_Count + 1'b1; end
   else begin FunStartSig_r <= 2'b10; inSRAM_Addr_r <= 18'd3; end
   
  3: begin WrData_r <= 16'haa55; j_Count <= j_Count + 1'b1; end
  
  4: if(RdWrDoneSig_w) begin FunStartSig_r <= 2'b00; j_Count <= j_Count + 1'b1; end
   else begin FunStartSig_r <= 2'b01; inSRAM_Addr_r <= 18'd34; end
  
  5: begin RdData_r <= RdData_w; j_Count <= j_Count + 1'b1; end
  
  6: if(TxDoneSig_w) begin TxEnSig_r <= 1'b0; j_Count <= j_Count + 1'b1; end
   else begin TxEnSig_r <= 1'b1; TxData_r <= RdData_r[7:0]; end
  
  7: if(m_Count == T1s) begin m_Count <= 26'd0; j_Count <= j_Count + 1'b1; end
   else begin m_Count <= m_Count + 1'b1; end
  
  8: j_Count <= 4'd0;
 endcase

assign FunStartSig_w = FunStartSig_r;
assign inSRAM_Addr_w = inSRAM_Addr_r;
assign WrData_w = WrData_r;
assign TxEnSig_w = TxEnSig_r;
assign TxData_w = TxData_r;

endmodule

最后还有串口建模代码，想看着留言，时间不早了，睡了，否则对不起自己，呵呵…