原创 3D IC manufacturing gets ready for "prime time"

In 2012, technology for 3D IC integration and packaging has not only moved from 'lab to fab,' but is on the cusp of high volume commercial manufacturing of a first wave of 3D IC products in 2013 and beyond. A convergence of economic, market and technology forces has led to 3D IC technology breakthroughs by global semiconductor leaders, including Intel, IBM, Micron, Qualcomm, Samsung, ST-Microelectronics and Xilinx.
 

In a quest to leap ahead of Moore's Law to address growing demand for smarter, more highly integrated, lower power electronic systems for myriad applications—driven by the so-called "Internet of Things"—a short list of companies is proving the viability of 3D IC manufacturing based upon through silicon via (TSV) technology and leveraging brand new supply chain models.

Industry pioneers are overcoming the limitations of Moore's Law to deliver unprecedented capacity and performance, paving the way for a new class of heterogeneous ICs that can mix and match different types of die (e.g. processors, memories, FPGAs, analogue) to create SoCs that have never been possible before.

Xilinx's Stacked Silicon Interconnect (SSI) 3D IC architecture facilitates communication between multiple dice placed side-by-side on top of a passive silicon interposer. Both programmable logic and transceiver mixed-signal dice are integrated with over 10,000 programmable interconnects through the silicon interposer, providing double the design capacity, system-level performance, and integration of a purely monolithic device.

The 3D die stacking technology increases aggregate inter-chip bandwidth and shrinks board footprint while reducing I/O latency and energy consumption. By integrating in one package multiple tightly-coupled semiconductor dice, this technology gives system designers additional options to partition and scale solutions efficiently.
In parallel to these efforts, we see DRAM manufacturers use TSV technology to initially deliver standalone packaged stacked devices. DRAM manufacturers are also active in standards committees specifying Wide I/O DRAM which is targeted at interposer and active on active mobile devices. Work is also well along in specifying higher bandwidth 3D IC DRAM standards, which are more suitable for computing and network applications.

On the supply chain front, TSMC demonstrated the commercial viability of its chip on wafer on substrate (COWOS) technology in preparation for the launch of 3D IC assembly services as a general offering in 2013.
So, what challenges are ahead for mainstream delivery and adoption of 3D ICs in 2013 & beyond?

To fully realize the promise of 3D ICs, our industry faces a variety of technological and business obstacles. First and foremost is to reduce the cost of the interposer and assembly process. Much of these improvements will come from volume adoption, but it is also critical that a healthy open market be created in these technologies and services. Secondly, we need to design in Known Good Die (KGD) and more specifically Known Good Bin capabilities that maximise the probability that a 3D IC will meet all of its specs after assembly. Thirdly, we need to develop new business models that allow die from a number of companies to be assembled by an integrator with cost structure, supply chain, yield/ownership and liability all specified in advance so we can maximize the range of applications that can be addressed by the technology.

Already, Xilinx R&D efforts are well underway for a second generation of 3D IC advancements, leaping ahead of Moore's Law once again to inspire engineers to invent ever smarter, more integrated, bandwidth-hungry systems with fewer chips, faster.

In 2013 and beyond, Xilinx is committed to extending the value and proliferation of 3D IC technology in partnership with a growing ecosystem of foundry, EDA, supply chain, semiconductor, IP and systems companies to drive radical improvements in system-level IC integration for tomorrow's electronic system designs.

- Liam Madden, Corporate VP, Xilinx Inc.