原创 追求简化意味着让FPGA免费？

A month ago, we gently chided Technology Review for getting all starry-eyed over the new Tabula architecture, as though large numbers of design engineers would actually use on-the-fly reprogrammability (http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/instant-fpga-fashion-change-except-when-it-isn%E2%80%99t). Nothing specific was missing in the Tabula architecture, mind you, it’s just that visionaries had been predicting FPGA users’ interest in in-system reprogrammability for 20 years, only to hear collective yawns. Now, we have Ron Wilson, editorial director at EDN, coming along to dash cold water on the entire FPGA design process (http://www.edn.com/article/518117-FPGAs_try_to_get_embedded.php). Wilson cited numbers from the “Mind of the Engineer” study showing fewer engineers considering FPGAs.

How is this to be reconciled with recent internal numbers at the FPGA market leaders that 2011 growth rates are in excess of 30 percent? Actually, it’s perfectly reasonable to assume both trends are true. The paradox is similar to that seen in handheld wireless use among consumers.

To the committed smartphone user (and the market analyst following such users), the only issue is the relative boom in iPhone vs. Android platforms. To the committed pioneers, the large number of cell phone users who choose to stick with a 2G or 3G phone for reasons of subscriber costs, difficulty in device use, etc. are non-persons scarcely worth consideration. Yet those who stick with the tried-and-true can represent a considerable continuing user base.

If you are an active user of FPGAs, you are seeing the unit price of mid-range FPGAs drop considerably, even as the performance of high-end devices soars to challenge the highest-end DSPs and CPUs. You also are seeing the design environments of schematic capture and simulation tools decline to blue-light-special levels, led in some cases by FPGA vendors themselves, like Lattice Semiconductor. New system-level tools from independent EDA companies, like the Corus suite from Veridae, allow complex observability across multiple FPGAs and standard devices.

If you’re used to slapping a standard MCU on a PCI Express board with a standard Ethernet MAC, sensor subsystem, memory controller, and serial interface controller, you’re not going to be aware of any of those trends, or care to investigate them. Price trends in mid-range ASSPs are trending down faster than FPGAs, and conservative engineers tend to stick with known entities.

But those who stick with familiar environments tend to be blind-sided by major paradigm shifts that catch them unawares. If you’re always sticking with Microchip, ST, or Freescale controller designs in the embedded realm, for example, you may be surprised to find the dominance that ARM now enjoys in embedded cores. And you may be unprepared when a customer demands that a next-generation design is ARM-compatible.

From the vantage point of examining next-generation consumer, industrial, and mil-aero applications, FPGAs seem to be doing a better job making inroads into former MPU and DSP realms than might have been anticipated five years ago. They are not being used for in-system reprogrammability, but for simple SoC function consolidation. But many design engineers will remain blithely unaware of such design trends, and will offer one more rev of MCU-plus-Ethernet-plus-USB ASSP until they are run over by the Mack truck representing the next generation in design.

原文：Does Keeping it Simple Mean Keeping It FPGA-Free?