原创 更高的协议为Altera定义高速互联

Altera Corp. is discovering that, even as the world centers on Ethernet and TCP/IP as the dominant protocols for high-speed communications, FPGA vendors nevertheless are being tasked with more and more support IP for protocols that extend up to the application layer.  Altera has been in the lead at developing mixed-signal Serdes (serializer-deserializer) devices at 10 and 28 Gbits/sec, but the Serdes IP at the heart of a transceiver is only the baseline foundation.

Paul Ekas, director of product planning at Altera, said that as quickly as groups such as IEEE, ITU, Metro Ethernet Forum, and Optical Internetworking Forum define new protocols for multi-gigabit communications, customers expect to see soft-configured support for those protocols in FPGAs.  The good thing for vendors and customers alike is that there is little call for hard-wiring such support in hard IP blocks, because of the rapid pace at which such protocols change.  Therefore, FPGA vendors can update libraries quickly and customers can enjoy flexibility in implementation.

The high-speed backbone world may look a lot simpler than 10 or 15 years ago, when networks were divided among Sonet, ATM, and Ethernet segments.  Today, Ethernet rules the roost in both enterprise and public carrier networks.  But the simplicity is only superficial.  Specialized high-speed links for storage and server clusters, such as Infiniband and Fibre Channel, might seem to be “also ran” at first glance, but Ekas said the tremendous size of deployed networks make it absolutely essential that Altera pursue such network protocols to new speed ranges above 10 Gbits/sec.

Ethernet also is a trickier multi-layer protocol than it was when relegated to the LAN in the 1990s.  Today, FPGA vendors must follow Layer 2 services such as E-LAN, E-Line, and PWE3.  They must understand a variety of encapsulation mechanisms residing at the MPLS layer and above.  And they must understand where physical-layer interfaces use the follow-on standard to Sonet, the Optical Transport Network.  This is where Altera’s 2010 acquisition of Avalon Microelectronics (http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/central-role-otn), Ekas said.

Two other trends deserve watching at the physical layer.  A variety of multiplexing options will arise as Ethernet moves to 40 and then 100 Gbits/sec.  For the higher speed, the most popular channel alternatives seem to be 4 x 25 Gbits and 10 x 10 Gbits.  FPGA vendors must be able to support transceiver module manufacturers with full channel support.  As an aside, Ekas said that 40-Gbit Ethernet now seems to be “only a stepping stone on the way to a quick 100-Gbit rollout – but it is an important stepping stone that cannot be bypassed in FPGA design.”

Altera is working with customers to determine which markets might benefit from the on-chip integration of TOSA and ROSA (transmit and receive optical subassembly) circuits, which Altera discussed with international journalists in early 2011 (http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/future-may-be-light-dark-corners-are-commonplace).  For the near-term foreseeable future, the customers interested in optical links directly on board on FPGA may be limited to those working on optical connections inside a single system, Ekas said.  Eventually, however, putting a TOSA and ROSA directly on an FPGA may allow the shrinking or elimination of the bulky modular optical transceivers used in many LAN and WAN designs – and that would be a relief to many in the communication market, Ekas said.