原创 Lattice依靠中端产品，平衡设计与外包

Lattice Semiconductor做出了一个很有意思的决定，公司将不再依赖高端性能和高密度的产品，而转向中端FPGA和高性能、低密度CPLD产品。莱迪思新上任的CEO Darin Billerbeck在全球性的巡演中向分析师和客户展示了这种战略上的改变，将给公司带来28%的季度性增长。

Lattice Semiconductor Corp. made a conscious decision before Darin Billerbeck joined as CEO that the company would dispense with the high end of performance and density in favor of mid-range FPGAs and high-performance, low-density CPLDs. Billerbeck has just returned from a world tour to show analysts and customers that such a strategy has a predictable quarterly growth rate of 28 percent.

“This was a conscious decision, in looking at the future of ECP3, to use a design with less routing and less dense lookup tables,” Billerbeck said. “We think we made the right call.” At the same time, he added, Lattice is developing its LUT6 architecture that can scale to 1 million lookup tables.

Lattice also brought a nuanced message of global sourcing to its market followers outside the U.S., where Lattice currently realized 82 percent of its sales. The largest chunk, 53 percent, comes from Asia excluding Japan, 8 percent comes from Japan, while 21 percent comes from Europe. The largest end-market sector for Lattice comes from communications, which 44 percent of its sales, followed by industrial at 31 percent, computing at 13 percent, and consumer at 12 percent.

Perhaps one of the most important signs of stability is Lattice’s lack of reliance on two or three large OEMs for the bulk of its sales. The top five Lattice customers account for 27 percent of sales, followed by the next 45 customers, accounting for 34 percent. That leaves 39 percent of the company’s business coming from customers ranking under Lattice’s Top 50.

Lattice vice president of marketing Doug Hunter said the global tour in May emphasized for foreign analysts that Lattice was not making a pell-mell move to offshore sources for manufacturing and back-end design processes. Instead, it is streamlining its design steps in the U.S. and the links between U.S. and offshore sites, while keeping critical steps in FPGA design within the U.S.
As part of this process, the former Agere/Lucent FPGA design site in Pennsylvania is no longer a design center, though it retains application and marketing employees. Design teams in California and Oregon will link more closely with Asia manufacturing sites to bring in new packaging capabilities, such as vertical stacking and side-by-side bonding, at the same time Lattice moves to smaller feature sizes.

One thing Lattice wants to emphasize to a bigger extent, in order to expand computing and consumer applications, is the product line it has developed for power management and clock management. These ASSPs, such as Power Manager II and ispClock, can be combined with both FPGA and CPLD families to create true Systems on a Chip. The strategy of using core designs to build up SoCs and ASSPs is what Lattice calls its “Platform and Derivatives” effort.

Billerbeck’s past experience as CEO of Zilog, before it was acquired by Ixys Corp., indicates he knows how to play the SoC derivatives game. What has heartened him since joining Lattice in late 2010, he said, is how well customers seem to understand the role that FPGAs and CPLDs play in just such a strategy.