原创 My favorite quirky chips (Part 1)

In some of my previous blogs, I outlined the history of the microprocessor. Two of the important developments were the Williams tube and the Whirlwind computer. Although the Whirlwind originally did use Williams tubes, it became the first machine with core memory. After those articles appeared, I visited London's Science Museum and took pictures of a Williams tube and a Whirlwind core plane (shown right). Alas, my camera skills are very poor, but the crude memory densities are startling: each of those cores, spaced about a quarter of an inch apart, stored a single bit.

Let's conclude this series by looking a few of the quirky microprocessors that came to life in the last forty years.

Motorola's schizophrenic device
Motorola's MC14500
64bit CPUs and VLIW architectures slam massive amounts of data around via wide parallel buses. Processors today are so fast and so hungry for data that chip designers do horrible things to push bits into the CPU as quickly as possible. But at one time, a narrow bus was seen as a competitive advantage.

Motorola's MC14500 was a one-bit CPU the company called an "Industrial Control Unit." The device's handbook has the intriguing statement: "When a job is dominated by calculations or data logging, a multibit processor is appropriate. When the task is decision and command oriented, a one-bit machine is an excellent choice."

I can't determine when the chip came to market, but the handbook is dated 1977. Revision 3 of the datasheet was released in early 1994, so these odd devices did gain some traction. Rumor has it they were used in some HVAC systems and in a lot of ladder-logic applications. Indeed, the part's handbook goes on at great length about implementing ladders in MC14500 assembly language.

This was a very early Harvard architecture part in that there were two buses: one 4 bits wide for instructions and a single-bit data bus. So, although the "one-bit" moniker is somewhat correct, the device was a bit schizophrenic.

The MC14500's 16 instructions did not include any arithmetic operations. No add, subtract, or the like. Instead, it included some simple loads and stores, ANDs and ORs, a jump, a single conditional skip, and a few instructions to control hardware. (It's possible to do arithmetic using just logical instructions.) Only a single register—the Results Register—existed, and that was, of course, just a bit wide.

This part was so quirky it didn't have a program counter. Designers were expected to create one external to the CPU. Its width was, well, anything the developer wanted. Running a tiny bit of code? Maybe an 8bit PC was appropriate. Or 32 bits for those applications needing 4 GN (giga-nibbles) of powerhouse processing.

So the inevitable question is "how did a jump work?" That was entirely up to the engineer crafting the circuits. The output enabling instruction (OEN) could be used to disable any changes occurring on the output data; at the end of a loop, assert OEN and let the machine execute whatever instructions—hopefully NOPs—remained until the PC rolled over. There was a JMP, but that instruction simply toggled an output bit. The design engineer was supposed to make that signal do something useful, like load the PC with some address.

As they would say here in Finksburg: "them boys at Motorola musta been smokin' somethin' illegal."
(The MC14500B's data sheet can be found here www.brouhaha.com/~eric/retrocomputing/motorola/mc14500b/mc14500brev3.pdf, and the part's handbook is here www.brouhaha.com/~eric/retrocomputing/motorola/mc14500b/mc14500b_icu_handbook.pdf.) Figure 1 shows the MC14500B block diagram.

Rad-hardened, but a speed cripple
RCA's 1802
RCA (Radio Corporation of America) had been selling a processor using a pair of chips but in 1976 merged the two onto a single die. The 1802 is apparently still available, now from Intersil.

Not nearly as quirky as the MC14500, the 1802 had a pretty conventional architecture. In fact, with 16 registers, this 8bit device was in some ways an improvement over contemporary parts. Each was 16bits wide in an era when competing CPUs had a few 8bit registers and maybe a couple of special-purpose wider ones for indexing. The Z80, for instance, had a pair of 16bit index registers and a clumsy way to gang some of the byte-wide registers in pairs.

Handling so many registers with an 8bit instruction was problematic, so the 1802 had several 4bit pointer registers. Instructions indexed into the register set via these, and there were a slew of instructions used to load, store, and otherwise manipulate the pointers. So, for example, an OR would combine the register indicated by the X pointer with the accumulator, annoyingly named "D," presumably for "Data." And, yes, the mnemonic for the Set X instruction was exactly what you're thinking.

Any of the 16 registers could be the program counter, which implies that one could do all sorts of interesting math on the PC. That made table-dispatching quite simple, and not a few developers wrote code so that data on an input port could immediately cause a change in control.

Lots of short branches were provided, but they were somewhat odd. Usually these sorts of instructions allow jumping from the PC plus or minus a certain amount (say, 127B ahead or back). On the 1802, the short branches just loaded the low byte of the PC with a new value, so the range of the branch varied depending on where the instruction was in memory. Patch in a few instructions and you might have a lot of rewriting to do as succeeding branches could no longer reach their destinations.

But one branch did not exist. There was no call instruction so a variety of tricks were used to invoke subroutines. When a program had only a handful of subroutines it was very efficient to assign a register to be each procedure's PC; other, rather clunky, approaches were used for bigger code bases.

Today we draw a pretty strong line between CPUs and microcontrollers. The former are naked processors while the latter include some mix of I/O and memory. The 1802 had a little built-in I/O, which was not called such. Four "EF" pins and one "Q" were parallel I/O ports, and dedicated branch instructions sampled these.

It's a little hard to believe today, but once MOS (metal oxide semiconductor) logic was considered a poor substitute for bipolar, as it was very slow. RCA was an early MOS pioneer and had a popular line of logic called the CD4000 series. What the technology did give was a wide voltage range and astonishingly low power requirements. In the 1970s, the bipolar people (uh, those who were not bipolar) were straightjacketed into slavish obedience to five volts with little tolerance for deviation. The 1802, being MOS (RCA called it COSMOS, later shortened to CMOS) tolerated a wide Vcc range. That, plus the low power, made it ideal for battery-operated applications.

To further cripple the 1802's speed, it used at least 16 clock cycles per instruction. 1802s were widely used in space since it was one of the first rad-hardened microprocessors available. And at the bottom of the ocean—we used 1802s in deep-sea probes that had to run for months on a few AAs. (The 1802's datasheet is here: http://homepage.mac.com/ruske/cosmacelf/cdp1802.pdf).

Signetics and more
Signetics' 8X300
In the mid-1970s, Scientific Micro Systems developed a part they called the SMS300, which Signetics manufactured. Eventually Signetics bought the rights to the device and renamed it the 8X300. It was sort of a predecessor to the digital signal processor, and, being built with bipolar Schottky transistors, was very fast for the time. The datasheet (http://datasheets.chipdb.org/Signetics/8X300/8X300_1977.pdf) pegs the operating speed at a blistering 8MHz, resulting in a 250 nsec instruction time. Yet to achieve that speed, memory accesses could not exceed 65 nsec.

For reasons that completely elude me Signetics called the 8X300 a "microcontroller," yet there was neither memory nor I/O on-board. At one point the datasheet refers to it as an "interpreter."