原创 Multicore in Networking

Networking gear companies are bullish about the multicore processors and are seeing tangible benefits from them. Let us look at the reasons for the same.

If we look at a networking equipment like router it has two broad components: the data plane and  control plane

The data plane is also referred as the fast path. This is the code that gets executed when a packet (like ethernet packet) comes on an interface like ethernet port. It is a real-time task and throughput of the system depends on this code. It is not a complex logic but it is typically handcrafted for higher throughput. It does not need much OS support. To process a packet, it refers the the “forwarding table” which is set up by control plane.

The second component is the Control Plane, also referred as slow path. It contains code for different protocols, that perform many functions like updating new routes, processing control packets and setting up forwarding tables which is accessed by datapath. If route from A to B is broken, it means a route is changed, and forwarding tables need to be changed to reflect that. This code is typically large, runs on top of an OS, runs infrequently, and is compute intensive.

In the early days, designers used to have same CPU handling both data plane and control plane leading to poor performance. If higher priority is given to the control plane against the data plane, processing of packets gets delayed , which leads to packet queueing, congestion and packet drops. If data plane gets higher priority than the control plane, then the  line events (e.g. link up/down) or the control plane indications (e.g. route change) get analysed lated.

To avoid this, system designers used to have two processors, one for control plane and other for data plane. Control process runs the routing protocols, computes the forwarding tables, and updates the same for data plane processor. But this had consequence of increased cost.

Now, multicore processors allow running of control plane protocols on a single core and allow running of  data plane code on other cores.

Availability of cheap cores has helped data plane immensely. Since the packet processing algorithm is essentially similar for all packets, it allows the partitioning of code to use the multiple cores and get performance boost.

First way of partitioning of data plane works like this: Suppose the dataplane code has 3 logical functions f1(), f2() and f3(). Now we can write the code in such a way that first core runs f1() and passes control to second core to run f2() and third core to run f3(). In this “pipelining”, the number of packets currently under processing is equal to the number of cores in the pipeline. By designing this pipeline efficiently, we can increase throughput multiple times.

The alternative to this partitioning is to have all the cores run the same code that read packets from the same input stream and write to the same output stream. Whichever core is free, picks up the next packet from input stream for processing. The full functionality of the packet processing pipeline is applied on the input packets by a single stage as opposed to sending the packets from one stage to another. It is also possible to have a hybrid model, where both models can be combined.

To summarize, the availability of multicore processors is a big blessing for for networking gear designers. It allows them to partition code efficiently (control and data plane codes) and also get performance boost by using pipelining in data plane code to get higher throughputs.

Semicon companies like Cavium, Tilera, Freescale all have multicore network processors and have helped to develop better networking gear for market.