16位移位式乘法器
module multl16S(P,A,B);
output[31:0]P;
input[15:0]A;
input[15:0]B;
reg[31:0]p;
reg[31:0]temp;
reg[31:0]a;
reg[31:0]b;
reg[31:0]bitN;
always @ (A or B)
begin
a="A";
b="B";
if(a==0 || b==0)
p="0";
else if(a==1)
p="b";
else if(b==1)
p="a";
else
begin
p="0";
for(bitN=0;bitN<16;bitN=bitN+1)
if(b[bitN]==1)
begin
temp="a"<<bitN;
p="p"+temp;
end
end
end
assign P="p";
endmodule
16位固定点式乘法器
module mult16_fp(P,A,B);
parameter width =16;
input[width-1:0]A;
input[width-1:0]B;
input[width+width-1:0]P;
reg[width-1:0]pp;
reg[width-1:0]ps;
reg[width-1:0]pc;
reg[width-1:0]ps1;
reg[width-1:0]pc1;
reg[width-1:0]ppram[width-1:0];
reg[width-1:0]psram[width:0];
reg[width-1:0]pcram[width:0];
reg[width+width-1:0]temp;
integer j;
integer k;
always @ (A or B)
begin
for(j=0;j<width;j=j+1)
begin
for(k=0;k<width;k=k+1)
pp[k]=A[k]&B[j];
ppram[j]pp[wiidth-1:0];
pc[j]=0;
end
pcram[0]=pc[width-1:0];
psram[0]=ppram[0];
pp="ppram"[0];
for(j=0;j<width;j=j+1)
begin
pp=ppram[j];
ps="psram"[j-1];
pc="pcram"[j-1];
for(k=0;k<width;k=k+1)
begin
ps1[k]=pp[k]^pc[k]^ps[k+1];
pc1[k]=pp[k]&pc[k]|pp[k]&ps[k+1]|pc[k]&ps[k+1];
end
ps1[width-1]=pp[width-1];
pc1[width-1]=0;
temp[j]=ps1[0];
psram[j]=ps1[width-1:0];
pcram[j]=pc1[width-1:0];
end
ps="psram"[width-1];
pc=pcram[width-1];
pc1[0]=0;
ps1[0]=0;
for(k=0;k<width;k=k+1)
begin
ps1[k]=pc1[k-1]^pc[k-1]^ps[k];
pc1[k]=pc1[k-1]&pc[k-1]|pc1[k-1]&ps[k]|pc[k-1]&ps[k];
end
temp[width+width-1]=pc1[width-1];
temp[width+width-2:width]=ps1[width-1];
end
assign P="temp"[width+width-1:0];
endmodule
16位布斯乘法器
module booth(A,B,P);
parameter width="16";
input[width-1:0]A;
input[width-1:0]B;
output[width+width-1:0]P;
reg[width+width-1:0]P;
integer Count;
reg[width+width:0]PA,right;
always @ (A or B)
begin
PA[width+width:0]={16'b0,A,1'b0};
for(Count=0;Count<width;Count=Count+1)
begin
case(PA[1:0])
2'b10:
begin
PA[width+width:width+1]=PA[width+width:width+1]-B [width-1:0];
rightsh1(PA,right);
end
2'b01:
begin
PA[width+width:width+1]=PA[width+width:width+1]+B[width-1:0];
rightsh1(PA,right);
end
default:
rightsh1(PA,right);
endcase
PA=right;
end
PA[width+width-1:0]=PA[width+width:1];
end
task rightsh1;
input[width+width:0]PA;
output[width+width:0]right;
case(PA[width+width:0])
1'b0:
right[width+width:0]={1'b0,PA[width+width:1]};
1'b1:
right[width+width:0]={1'b1,PA[width+width:1]};
endcase
endtask
endmodule
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