原创 vhdl语言 4位加法器程序

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-- 4-bit binary adder using integer math --
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LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY 4b_adder IS

PORT
(
   a_string     : IN INTEGER RANGE 0 TO 15;
   b_string     : IN INTEGER RANGE 0 TO 15;
   sum_string     : IN INTEGER RANGE 0 TO 31;
);

END 4b_adder ;

ARCHITECTURE arc OF 4b_adder IS

sum_string<=a_string+b_string;

END arc;